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never stop thinking. data sheet, rev. 1.07, nov. 2005 communications ADM7001/x single ethernet 10/100m phy
edition 2005-11-25 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
template: template_a4_3.0.fm / 3 / 2005-01-17 trademarks abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10 bases?, easyport?, vdslite? are trademarks of infi neon technologies ag. microsoft ? is a registered trademark of microsoft corporation, linux ? of linus torvalds, visio ? of visio corporation, and framemaker ? of adobe systems incorporated. single ethernet 10/100m phy revision history: 2005-11-25, rev. 1.07 previous version: page/date subjects (major change s since last revision) 2003-03-05 rev. 1.0: first release of ADM7001 2003-04-08 rev. 1.01: register modifications and pin updates 2003-07-24 rev. 1.02: the following sections were updated: 1.2, 1. 3, 2.1, 2.2.1, 2.2.5, 2. 2.7, 2.2.8, 2.2.8, 4.1, 4.2.3-4, 4.2.11-12, 4.3.4, 4.3.9, 4.3.11, 4.3.12, & 4.3.16 2003-07-30 rev. 1.03: updated section 6.2 2003-09-15 rev. 1.04: updated section 2.2.5, 2.2.8, & 4.2.11 2004-02-19 rev. 1.05: updated table 5.3 2004-04-16 rev. 1.06: removed tqfp packaging 2005-09-12 rev. 1.07 when changed to the new infineon format 2005-11-25 minor change. included green package information
data sheet 4 rev. 1.07, 2005-11-25 ADM7001/x data sheet table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.1 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 twisted pair interface, 5 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 digital ground/power, 7 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 ground and power, 5 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.4 clock input, 2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.5 mii/rmii/gpsi interface, 16 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.6 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.7 clock signals, 6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.8 led interface, 4 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.9 regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 10/100m phy block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.1 100base-x module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.2 100base-tx receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.3 100base-tx transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.4 100base-fx receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.5 100base-fx transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.6 10base-t module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.7 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.8 manchester encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.9 transmit driver and receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.10 smart squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.11 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1.12 collision detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1.13 jabber function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.14 link test function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.15 automatic link polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.16 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.17 auto negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.18 auto negotiation and speed configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 mac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.1 reduced media independent interface (rmii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.2 receive path for 100m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.3 receive path for 10m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.4 transmit path for 100m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.5 transmit path for 10m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.6 media independent interface (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table of contents
data sheet 5 rev. 1.07, 2005-11-25 ADM7001/x data sheet table of contents 3.2.7 receive path for mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.8 transmit path for mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.9 general purpose serial interface (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.10 receive path for gpsi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.11 transmit path for gpsi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3 led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4 management register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.1 preamble suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.2 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.6 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 dc characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.2.1 dc characte ristics for 2.5 v operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.2.1 xi/osci (crystal/oscillator) timing (in mii mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3 rmii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.1 refclk input timing (xi in rmii mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.2 refclk output timing (clko50 in rmii mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.3 rmii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.4 rmii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4 mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.1 rxclk clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.2 mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.4.3 txclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.4.4 mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5 gpsi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.1 gpsi receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.2 gpsi transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.6 serial management interface (mdc/mdio) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 5.7 power on configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
data sheet 6 rev. 1.07, 2005-11-25 ADM7001/x data sheet list of figures figure 1 ADM7001/x block diagram 10 figure 2 pin diagram 11 figure 3 100base-x block diagram and data path 27 figure 4 10base-t block diagram and data path 32 figure 5 rmii signal diagram 35 figure 6 rmii reception without error 35 figure 7 rmii reception with false carrier (100m only) 36 figure 8 rmii reception with symbol error 36 figure 9 10m rmii receive diagram 36 figure 10 100m rmii transmit diagram 37 figure 11 10m rmii transmit diagram 38 figure 12 mii signal diagram 39 figure 13 mii receive without error 39 figure 14 mii receive with false carrier 40 figure 15 mii receive with symbol error(100m only) 40 figure 16 mii transmission 41 figure 17 mii transmit with collision (half duplex only) 41 figure 18 gpsi signal diagram 42 figure 19 gpsi receive diagram 42 figure 20 gpsi transmit diagram 43 figure 21 smii read operation 44 figure 22 smii write operation 45 figure 23 medium detect power management flow chart 46 figure 24 power and ground filtering 47 figure 25 crystal/oscillator timing 75 figure 26 refclk input timing 76 figure 27 refclk output timing 77 figure 28 rmii transmit timing 78 figure 29 rmii receive timing 78 figure 30 rxclk output timing 79 figure 31 mii receive timing 81 figure 32 txclk output timing 82 figure 33 mii transmit timing 83 figure 34 gpsi receive timing 84 figure 35 gpsi transmit timing 84 figure 36 serial management interface (mdc/mdio) timing 85 figure 37 power on configuration timing 86 figure 38 ADM7001/x,low profile q uad flat package (lqfp) 87 list of figures
data sheet 7 rev. 1.07, 2005-11-25 ADM7001/x data sheet list of tables table 1 abbreviations for pin type 12 table 2 abbreviations for buffer type 12 table 3 twisted pair interface, 5 pins 13 table 4 digital ground/power, 7 pins 14 table 5 ground and power, 5 pins 15 table 6 clock input, 2 pins 16 table 7 mii/rmii/gpsi interface, 16 pins 16 table 8 reset pin 22 table 9 clock signals, 6 pins 22 table 10 led interface, 4 pins 24 table 11 regulator control 25 table 12 look-up table for translating 5b symbols into 4b nibbles 28 table 13 channel configuration 38 table 14 speed led display 43 table 15 duplex led display 43 table 16 activity/link led display 43 table 17 cable distance led display 44 table 18 registers address space 48 table 19 registers overview 48 table 20 registers access types 48 table 21 registers clock domains 49 table 22 reserved registers 59 table 23 absolute maximum rating 74 table 24 recommended operating conditions 74 table 25 dc characteristics for 2.5 v operation 74 table 26 crystal/oscillator timing 75 table 27 refclk input timing 76 table 28 refclk output timing 77 table 29 rmii transmit timing 78 table 30 rmii receive timing 79 table 31 refclk input timing 80 table 32 mii receive timing 81 table 33 txclk output timing 82 table 34 mii transmit timing 83 table 35 gpsi receive timing 84 table 36 gpsi transmit timing 85 table 37 serial management interface (mdc/mdio) timing 85 table 38 power on configuration timing 86 table 39 dimensions for 100 pin lqfp package 88 list of tables
ADM7001/x data sheet product overview data sheet 8 rev. 1.07, 2005-11-25 1 product overview features and block diagram. 1.1 overview the ADM7001/x is a single chip one port 10/100m phy, which is designed for toda y?s low cost and low power dual speed application. the ADM7001x is the envi ronmentally friendly ?green? package version. it supports auto sensing 10/100 mbps ports with on-chip clock recovery and ba se line wander correction including integrated mlt-3 functionality for 100 mbps operation, and also supports manchester code converter with on chip clock recovery circuitry for 10 mbps functionality. me anwhile, it provides medium independent interface (mii), reduced medium independent interface (rmii) and general purpose serial interface (gpsi), three different interfaces in different applications. for today's ia (information application), ADM7001/x supports "auto cross over detection" function to eliminate the technical barrier between networking and end user. with the aid of this auto cross over detection function, plug-n-play feature can be easily applied to ia relative products. the major design target for ADM7001/x is to reduce th e power consumption and system radiation for the whole system. with the aid of this low power consumption and low radiation chip, the fan and on-system power supply can be removed to save the total manufacture cost and make soho application achievable. 1.1.1 package information 1.2 features main features: ? ieee 802.3 compatible 10base-t and 100base-t ph ysical layer interface and ansi x3.263 tp-pmd compatible transceiver. ? single chip, integrated physical layer and tran sceivers for 10base-t and 100base-tx function. ? medium independent interface (mii), reduced mii (rmii) and general purpose serial interface (gpsi) for high port count switch. ? built-in 10 mbit transmit filter. ? 10 mbit pll, exceeding tolerances for both preamble and data jitter. ? 100 mbit pll, combined with the digital adaptive equalizer and performance up to 120 meters for utp 5. ?125 mhz clock generator and timing recovery. ? integrated base line wander correction. ? carrier integrity monitor function supported. ? supports fefi when auto negotiation disabled. ? supports auto mdix func tion for plug-and-play ? ieee 802.3u clause 28 compliant auto negotiation for full 10 mbit/s and 100 mbit/s control. ? supports programmable led for different switch application and power on led self test. ? supports cable length indication both in mii register and led (programmable) ? supports pecl interface for fiber connection. ? supports tp vs. fx medium converter function. ? supports fault propagation function for medium converter. ? supports 10k bytes jumbo packet with clock skew 150 ppm. product name product type package ordering number ADM7001/x ADM7001/x lqfp-48-1 q67801h 2a 1) 1) contact infineon for the updated ordering information
data sheet 9 rev. 1.07, 2005-11-25 ADM7001/x data sheet product overview ? built-in clock generator and power on reset signal to save system cost. ? 48 lqfp without regulator. ? supports power saving function. ? supports parallel led output.
ADM7001/x data sheet product overview data sheet 10 rev. 1.07, 2005-11-25 1.3 block diagram figure 1 ADM7001/x block diagram
data sheet 11 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription 2 interface description 2.1 pin diagram figure 2 pin diagram 2.2 pin description note: for those pins, which have multiple functions, pin name is separated by sl ash ("/"). if not specified, all signals are default to digital signals. please refer to table 1 pin type descriptions' for an explanation of pin abbreviations. vcco_25 gndik rxdv/crsdv/dis_amdix rmii_en/rx_clk isolate/rxer gndo vccik_25 txer txclk txen txd0 txd1 pwrdown_n anen/colled dupful/dupled spd100/spdled lnkact phyad0/intr vcco_2.5 gndo crs col/gpsi txd3 txd2 ADM7001l/t 48 pin gndik test1 xo xi vcc33in reset_n mdio mdc phyad1/rxd3 phyad2/rxd2 pyyad3/rxd1 phyad4/rxd0 vcc25out(core) txp txn gndpll vccpll_25 rtx test0 gndtr sd/fxen rxp rxn vcca_25
ADM7001/x data sheet interface de scription data sheet 12 rev. 1.07, 2005-11-25 table 1 abbreviations for pin type abbreviations description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. ao output. analog levels. ai/o input or output. analog levels. pwr power gnd ground mcl must be connected to low (jedec standard) mch must be connected to high (jedec standard) nu not usable (jedec standard) nc not connected (jedec standard) table 2 abbreviations for buffer type abbreviations description z high impedance pu1 pull up, 10 k ? pd1 pull down, 10 k ? pd2 pull down, 20 k ? ts tristate capability: the corres ponding pin has 3 operationa l states: low, high and high- impedance. od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to shar e as a wire-or. an external pull-up is required to sustain the inactive state until another agent drives it, and must be provid ed by the central resource. oc open collector pp push-pull. the corresponding pin has 2 operational states: active-low and active-high (identical to output with no type attribute). od/pp open-drain or push-pull. the corresponding pin can be configured either as an output with the od attribute or as an output with the pp attribute. st schmitt-trigger characteristics ttl ttl characteristics
data sheet 13 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription 2.2.1 twisted pair interface, 5 pins table 3 twisted pair interface, 5 pins pin or ball no. name pin type buffer type function 35 txp ai/o twisted pair transm it output positive 34 txn ai/o twisted pair transm it output negative 27 rxp ai/o twisted pair receive input positive 26 rxn ai/o twisted pair receive input negative 28 power on setting fxen ai fiber enable value on this pin will be la tched by ADM7001/x/x during power on reset as fiber select signal. 0 b , twisted pair mode 1 b , fiber optic mode fiber mode sdp 100base-fx signal detect. after power on reset stage, this pin acts as signal detect signal from external fiber optic transceiver in case fxen is detected as high during power on reset. 0 b , no signal detected 1 b , signal
ADM7001/x data sheet interface de scription data sheet 14 rev. 1.07, 2005-11-25 2.2.2 digital ground/power, 7 pins table 4 digital ground/power, 7 pins pin or ball no. name pin type buffer type function 6, 17 gndo d,gnd ground used by 3.3 v i/o. 2, 37 gndik d,gnd ground used by core. 1, 18 vcco_25 d,pwr 2.5v power used by digital i/o pad. 7 vccik_25 d,pwr 2.5 v power used by core
data sheet 15 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription 2.2.3 ground and power, 5 pins table 5 ground and power, 5 pins pin or ball no. name pin type buffer type function 41 vcc3in a,pwr 3.3v power input to ADM7001/x and used by built-in 3.3 v to 2.5 v regulator. 36 vcc25out a,pwr 2.5v power output by ADM7001/x. maximum supply current from this pin is 200 ma 29 gndtr a,gnd analog ground pad 25 vcca_25 a,pwr analog 2.5 v power 32 vccpll_25 a,pwr analog 2.5 v power used by clock generator module.
ADM7001/x data sheet interface de scription data sheet 16 rev. 1.07, 2005-11-25 2.2.4 clock input, 2 pins 2.2.5 mii/rmii/gpsi interface, 16 pins table 6 clock input, 2 pins pin or ball no. name pin type buffer type function 40 xi/osci i ctl crystal/oscillator input. 25m crystal/oscillator input in mii mode and 50m clock input in rmii mode (also called refclk in rmii mode). note: ctl: crystal 39 xo o ctl crystal output. when 25m oscillator is used , this pin should left unconnected. capable of driving one xi input for multiple port application. note: ctl: crystal table 7 mii/rmii/gpsi interface, 16 pins pin or ball no. name pin type buffer type function 9 mii mode txclk o 16ma mii transmit clock. 25m clock output in 100base-x mode and 2.5m clock output for 10base-t mode. this clock is continuously driven output and generated from xi. before speed is recognized, this pin drives out continuous 25m clock rmii mode txclk n/a gpsi mode txclk gpsi transmit clock. 10m clock output in 10base-t mode.
data sheet 17 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription 14, 13, 12, 11 mii mode txd[3:0] i ttl pd transmit data. nibble-wide transmit data stream in mii mode. these four bits are synchronous to the rising edge of txclk and txd[3] is the most significant bit rmii mode txd[3:0] di-bits transmit data. txd0 and txd1 for the di-bits that are transmitted and are driven synchronously to refclk . txd[1] is the msb. note that in 100mb/s mode, txd can change once per refclk cycle, whereas in 10mb/s mode, txd must be held steady for 10 consecutive refclk cycl es. txd[3] and txd[2] are not used in rmii mode, left unconnected or pull down externally for normal operation. gpsi mode txd[3:0] serial transmit data. txd0 for the designated port inputs the data that is transmitted and is driven synchronously to txclk in 10mb/s mode. when ADM7001/x is programmed into gpsi mode, txd[3:1] should be left unconnected or pull down externally for normal operation. 10 mii mode txen i ttl pd transmit enable. transmit enable to indicate that the data on txd[3:0] is valid. rmii mode txen transmit enable. txen indicates that the di-bit on txd is valid and it is driven synchronously to refclk. gpsi mode txen transmit enable. transmit enable to indicate th at the data on txd0 is valid. 8 mii mode txer i ttl pd transmit error. active high signal to indicate that there is error condition requested by mac. rmii mode txer transmit error. active high signal to indicate that there is error condition requested by mac. gpsi mode low keep low in gpsi mode. table 7 mii/rmii/gpsi interface, 16 pins (cont?d) pin or ball no. name pin type buffer type function
ADM7001/x data sheet interface de scription data sheet 18 rev. 1.07, 2005-11-25 4 power on setting rmii_en i lvttl pd rmii enable. used to select mii or rmii operation. the default value during power on reset is 0 (before rmii_en and gpsi value is determined) note: lvttl: low voltage ttl level 0 b , mii mode 1 b , rmii mode mii mode rx_clk o 16ma mii receive clock. 25m clock output in 100base-x mode, 2.5m clock output for 10base-t mii mode. this clock is recovered from the received data on the cable i nput. due to recovered from incoming receive data, it is possible that rxclk starts running yet rxdv keeps low for a while. during power on reset, there is no receivin g clock driven by ADM7001/x rmii mode clko50 rmii 50m clock output. this pin outputs continuous 50m clock in rmii mode. to reduce the bom cost for syst em application, user can connect this pin directly to refclk to proper rmii operation. gpsi mode rx_clk gpsi receive clock. 10m clock for 10base-t gpsi mode. this clock is recovered from the received data on the cable input. due to recovered from incoming receive data, it is possible that rxclk starts running yet crs keeps low for a while. during power on reset, there is no receiving clock driven by ADM7001/x. note: that clock on this pin will not be active during power on reset due to power on setting. table 7 mii/rmii/gpsi interface, 16 pins (cont?d) pin or ball no. name pin type buffer type function
data sheet 19 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription 3 power on setting dis_amdix_en i lvttl pd disable auto crossover function value on this pin will be latc hed by ADM7001/x to select auto cross-over function. note: lvttl: low voltage ttl level 0 b , enable auto crossover 1 b , disable auto crossover mii mode rxdv o 8ma mii receive data valid. active high signal to indicate that the data on rxd[3:0] is valid. synchronous to the rising edge of rxclk in mii mode. rmii mode crsdv rmii carrier sense/receive data valid. represents receive carrier se nse and data valid in rmii mode. crsdv asserts when the receive medium is non- idle. the assertion of crsdv is asynchronous to refclk. at the de-assertion of carrier, crsdv de-asserts synchronously to refclk only on the first di-bit of rxd. if there is still data in the fifo not yet presen ted onto rxd, then on the second di-bit of rxd, crsdv is asserted synchronously to refclk. the toggling of crsdv_p on the first and second di-bit continues until all the data in the fifo is presented onto rxd. crsdv is asserted for the duration of carrier activity for a false carrier event. gpsi mode low keep low in gpsi mode. 45, 46, 47, 48 power on setting phyad[1:4] i ttl pd phy address select value on these 4 pins co mbined with phyad0 will be stored into ADM7001/x as phy physical address during power on reset. after power on reset, these 4 pins are output. mii mode rxd[3:0] o 8ma mii receive data. nibble-wide receive data stream in mii mode. these four bits are synchronous to the rising edge of rx_clk and rxd[3] is the most significant bit. rmii mode rxd[1:0] rmii receive data. rxd0 and rxd1 for the di-bits that are received and are driven synchronously to refclk. rxd[1] is the msb. note that in 100mb/s mode, rxd can change once per refclk cycle, whereas in 10mb/s mode, rxd must be held steady for 10 consecutive refclk cycles. rxd[3:2] have not used in this mode. gpsi mode rxd gpsi receive data. rxd0 for the designated port inputs the data that is transmitted and is driven synchronously to rx_clk in 10mb/s mode. rxd[3:1] have not used in this mode. table 7 mii/rmii/gpsi interface, 16 pins (cont?d) pin or ball no. name pin type buffer type function
ADM7001/x data sheet interface de scription data sheet 20 rev. 1.07, 2005-11-25 5 power on setting isolate i ttl pd isolate value on this pin will be la tched by ADM7001/x during power on reset. 0 b , normal operation 1 b , all mii outputs are tri-st ated. all mii inputs(txd, txen, txer) are ignored mii mode rxer o 4ma mii receive error. active high signal to indicate that there is error condition detected by ADM7001/x. when error is detected, rxer will be high and maintains hi gh until rxdv is de-asserted. rmii mode rxer rmii receive error. active high signal to indicate that there is error condition detected by ADM7001/x. when error is detected, rxer will be high and maintains high until crsdv is de-asserted. gpsi mode n/a no operation in gpsi mode. 15 power on setting gpsi i pd gpsi mode select value on this pin will be sampled by ADM7001/x during power on reset to form gpsi internal control signal. together with rmii_en, these two pins form three possible internal supported by ADM7001/x. rmii_en gpsi interface 0 b , 0 b mii 0 b , 1 b gpsi(1m8) 1 b , x rmii gpsi/mii mode col o 8ma gpsi/mii collision in half duplex mode, active high to indicate that there is collision on the medium. in fu ll duplex mode, this pin will keep low all the time. rmii mode n/a not available table 7 mii/rmii/gpsi interface, 16 pins (cont?d) pin or ball no. name pin type buffer type function
data sheet 21 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription note: lvttl: low voltage ttl level 16 power on setting repeater i lvttl pd repeater mode. value on this pin will be la tched by ADM7001/x during power on reset as repeater mode note: lvttl: low voltage ttl level 0 b , sw/nic mode, crs will be asserted according to rx/tx in half duplex mode. 1 b , repeater mode. crs will be asserted only in rx mode in half duplex operation. mii mode crs o 8ma mii carrier sense. this bit indicates that there is carrier sense presented on the medium. note that in half duplex mode, this pin will also be asserted high by ADM7001/x under transmit condition. this pin is asynchronous to rx_clk. rmii mode n/a not available. gpsi mode crs gpsi carrier sense. this bit indicates that there is carrier sense presented on the medium. note that in half duplex mode, this pin will also be asserted high by ADM7001/x under transmit condition. this pin is asynchronous to rx_clk. table 7 mii/rmii/gpsi interface, 16 pins (cont?d) pin or ball no. name pin type buffer type function
ADM7001/x data sheet interface de scription data sheet 22 rev. 1.07, 2005-11-25 2.2.6 reset pin 2.2.7 clock signals, 6 pins table 8 reset pin pin or ball no. name pin type buffer type function 42 reset# i st reset signal active low to bring ADM7001/x into reset condition. recommend keeping low for at least 200 ms to ensure the stability of the system after power on reset. table 9 clock signals, 6 pins pin or ball no. name pin type buffer type function 43 mdio i/o lvttl pu management data. mdio transfers management data in and out of the device synchronous to mdc. note: lvttl: low voltage ttl level 44 mdc i lvttl management data reference clock. a non-continuous clock input for management usage. ADM7001/x will use this clock to sample data input on mdio and drive data onto mdio accord ing to rising edge of this clock. note: lvttl: low voltage ttl level 19 power on setting phyad0 i lvttl pu phy address bit 0. see rxd[3:0] description. note: lvttl: low voltage ttl level mii/rmii/gpsi mode intr# interrupt default active low signal to indica te that there is interrupt event in smi register. active value of interrupt signal can be configured by register 18.1. only available when interrupt mode is selected. note: lvttl: low voltage ttl level
data sheet 23 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription 24 pwrdown# i lvttl pu low power operation. note: when reset# is reset to 0 and pwrdown# is set to 0, whole ADM7001/x blocks will be disabled. 0 b , ADM7001/x in low power mode operation. all blocks except the energy detection and crystal oscillator are de- activated. 1 b , ADM7001/x in normal mode operation. note: lvttl: low voltage ttl level 38, 30 test[1:0] i lvttl pd industrial test pin. keeps low for normal operation. note: lvttl: low voltage ttl level table 9 clock signals, 6 pins (cont?d) pin or ball no. name pin type buffer type function
ADM7001/x data sheet interface de scription data sheet 24 rev. 1.07, 2005-11-25 2.2.8 led interface, 4 pins table 10 led interface, 4 pins pin or ball no. name pin type buffer type function 20 reserved i ttl pu reserved. lnkact o 8ma link/activity led. active low (note) 100ms (blink 100ms) to indicate that there is transmit or receive activity after link up. keeps high all the time when link is failed. 21 power on setting spd100 i ttl pu recommend 100m operation. this bit is only available in tp mode. together with anen to form speed mode select for ADM7001/x: anen spd100 mode 0 b , 0 b force 10base-t mode 0 b , 1 b force 100base-tx mode 1 b , 0 b 10m capability 1 b , 1 b 10/100m capability normal mode spdled o 8ma speed led.(note) 0 b , 100m 1 b , 10m cable length led. when fxen is low and mii register 18.2 dis_cablen_led is set to 0, this pin together with colled and lnkactled form cable length information on twisted pair note: that the following indication assume recommend value on spdled, coll ed and lnkactled is high, when corresponding bit's power on setting bit is 0, polarity of corres ponding bit will be inverted. spdled colled lnkactled cable length note: when recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high. 110 b , >140 meters or link failed 110 b , 0 - 40 meters 100 b , 40 - 80 meters 000 b , 80 - 120 meters xxx b , flashed reserved
data sheet 25 rev. 1.07, 2005-11-25 ADM7001/x data sheet interface de scription 2.2.9 regulator control 22 power on setting dupful i ttl pu duplex control this pin is only available when auto negotiation is disabled. anen dupful mode 0 b , 0 b force to half duplex mode 0 b , 1 b force to full duplex mode 1 b , 0 b half duplex capability 1 b , 1 b full/half duplex capability normal mode dupled o 8 ma duplex led.(note) note: when recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high. this rule also applies to cable length indication 0 b , full duplex 1 b , half duplex 23 power on setting anen i ttl pu auto negotiation enable. this bit is only available in tp mode. 0 b , disable auto negotiation 1 b , enable auto negotiation normal mode colled o 8ma collision led. keep high (note) when ADM7001/x is in full duplex mode and will blink 100 ms when co llision condition is detected in half duplex mode. note: when recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high. table 11 regulator control pin or ball no. name pin type buffer type function 31 rtx ai constant voltage reference. external 1.1k ? +/- 1% resistor connection to ground. table 10 led interface, 4 pins (cont?d) pin or ball no. name pin type buffer type function
ADM7001/x data sheet function description data sheet 26 rev. 1.07, 2005-11-25 3 function description ADM7001/x integrates 100base-x physical sub layer (p hy), 100base-tx physical medium dependent (pmd) transceivers, and complete 10base-t modules into a single chip for both 10 mbps and 100 mbps ethernet operations. it also supports 100base-fx operation through ex ternal fiber-optic transceivers. the device is capable of operating in either full-duplex mode or half-duplex mode in either 10 mbps or 100 mbps operation. operational modes can be selected by hardware configuration pins, soft ware settings of management registers, or determined by the on-chip auto negotiation logic. the 10base-t section of the device consists of the 10 mbps transceiver module with filters and a manchester endec module. ADM7001/x consists of seven kinds of major blocks: ? 10/100m phy block ? mac interface ? led display ?smi ? power management ? clock generator ? voltage regulator each 10/100m phy block contains: ? 10m phy block ? 100m phy block ? auto-negotiation ? other digital control blocks 3.1 10/100m phy block the 100base-x section of the device im plements the following functional blocks: ? 100base-x physical coding sub-layer (pcs) ? 100base-x physical medium attachment (pma) ? twisted-pair pmd (tp-pmd) transceiver the 100base-x and 10base-t sections share the following functional blocks: ? clock synthesizer module ? mii registers ? ieee 802.3u auto negotiation the interface used for communication between phy block and switch core is mii interface. 3.1.1 100base-x module ADM7001/x implements 100bas e-x compliant pcs and pma, and 100base-tx compliant tp-pmd as illustrated in figure 3 . bypass options for each of the major functional blocks within t he 100base-x pcs provide flexibility for various applications. 100 mbit/s phy loop back is included for diagnostic purpose. 3.1.2 100base-tx receiver for 100base-tx operation, the on-chip twisted pair receiver that consists of a differential line receiver, an adaptive equalizer and a base-line wander compensatio n circuits detects the incoming signal. ADM7001/x uses an adaptive equalizer t hat changes filter frequency response in accordance wi th cable length. the cable length is estimated based on th e incoming signal strength. the equa lizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable.
data sheet 27 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description the 100base-x receiver consists of fu nctional blocks required to recover and condition the 125 mbps receive data stream. the ADM7001/x impl ements the 100base-x rece iving state machine diagram as given in ansi/ieee standard 802.3u, clause 24. the 125 mbps receive data stream may originate from the on-chip twisted-pair transceiver in a 100base-tx application. alternatively, the receive data stream may be generated by an external optical receiver as in a 100base-fx application. the receiver block consists of the following functional sub-blocks: ? a/d converter ? adaptive equalizer and timing recovery module ? nrzi/nrz and serial/parallel decoder ?de-scrambler ? symbol alignment block ? symbol decoder ? collision detect block ? carrier sense block ? stream decoder block a/d converter high performance a/d converter with 125m sampling rate co nverts signals received on rxp/rxn pins to 6-bits data streams; besides it possess au to-gain-control capability that will further impr ove receive performance especially under long cable or harsh detrimental signal in tegrity. due to high pass char acteristic on transformer, built in base-line-wander correcting circui t will cancel it out and restore its dc level. figure 3 100base-x block diagram and data path adaptive equalizer and timing recovery module all digital design is especially immune from noise environments, and achieves better correlations between production and system testing. baud rate adaptive equa lizer/timing recovery comp ensates line loss induced from twisted pair and tracks far end clock at 125m sample s per second. adaptive equalizer implemented with feed

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ADM7001/x data sheet function description data sheet 28 rev. 1.07, 2005-11-25 forward and decision feedback techniques meets the requirement of ber less than 10-12 for transmission on cat5 twisted pair cable ranging from 0 to 140 meters. nrzi/nrz and serial/parallel decoder the recovered data is converted from nrzi to nrz. the data is not necessarily aligned to 4b/5b code group?s boundary. data descrambling the descrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering linear feedback shift register (lfs r) to the state of the scrambling lfsr. upon achieving synchronization, the incoming data is xore d by the deciphering lfsr and descrambled. in order to maintain synchronization, the descrambler co ntinuously monitors the validity of the unscrambled data that it generates. to ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status. upon synchronization of the descrambler the hold timer starts a 722 s countdown. upon detection of at least 6 idle symbols (30 consecutive 1) within the 722 s period, the hold ti mer will reset and begin a new countdown. this moni toring operation will continue indefinitely to give a pr operly operating network connection with good signal integrity. if the link state monitor does not re cognize at least 6 unscrambled idle symbols within 722 s period, the descrambler will be forced out of the current state of synchronization and reset in order to re-acqui re synchronization. symbol alignment the symbol alignment circuit in the ADM7001/x determines code word alignment by rec ognizing the /j/k delimiter pair. this circuit operates on unaligned data from the de scrambler. once the /j/k symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. symbol decoding the symbol decoder functions as a look-up table that tran slates incoming 5b symbols into 4b nibbles as shown in table 12 . the symbol decoder first detects the /j/k symbol pair preceded by idle symbols and replaces the symbol with mac preamble. all subsequent 5b symbols ar e converted to the corresponding 4b nibbles for the duration of the entire packet. this conversion ceases up on the detection of the /t/r symbol pair denoting the end of stream delimiter (esd). the translated data is presen ted on the internal rxd[3:0] signal lines with rxd[0] represents the least significant bit of the translated nibble. table 12 look-up table for translating 5b symbols into 4b nibbles pcs code-group[4:0] name mii (txd/rxd)<3:0> interpretation 11110 0 0000 data 0 01001 1 0001 data 1 10100 2 0010 data 2 10101 3 0011 data 3 01010 4 0100 data 4 01011 5 0101 data 5 01110 6 0110 data 6 01111 7 0111 data 7 10010 8 1000 data 8 10011 9 1001 data 9 10110 a 1010 data a 10111 b 1011 data b
data sheet 29 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description valid data signal the valid data signal (rxdv) indicates that recovered an d decoded nibbles are presented on the internal rxd[3:0] synchronous to receive clock, rxclk. rxdv is asserted when the first nibble of tr anslated /j/k is ready for transfer over the internal mii. it remains active until either the /t/r delimiter is recognize d, link test indicates failure, or no signal is detected. on any of these conditions, rxdv is deasserted. receive errors the rxer signal is used to communicate with receiver erro r conditions. while the receiver is in a state of holding rxdv asserted, the rxer will be asse rted for each code word which do es not map to a valid code-group. 100base-x link monitor the 100base-x link monitor function allows the receiver to ensure that reliable data is received. without reliable data reception, the link monitor will ha lt both transmit and receive operat ions until a valid link is detected. the ADM7001/x performs the link integrity test as out lined in ieee 100base-x (cla use 24) link monitor state diagram. the link status is multiplexed with 10 mbits/s link status to form the reportable link status bit in serial management register 1h, and driven to the lnkact pin. when persistent signal energy is detected on the netw ork, the logic moves into a link-ready state after approximately 500 s, and waits for an enable from the auto negotiati on module. when receiving, the link-up state 11010 c 1100 data c 11011 d 1101 data d 11100 e 1110 data e 11101 f 1111 data f 11111 i undefined idleused as inte r-stream fill code 11000 j 0101 start-of-stream delimiter, part 1 of 2; always used in pairs with k 10001 k 0101 start-of-stream delimiter, part 2 of 2; always used in pairs with j 01101 t undefined start-of-stream delimiter, part 1 of 2; always used in pairs with r 0111 r undefined start-of-stream delimiter, part 2 of 2; always used in pairs with t 00100 h undefined transmit error; used to force signaling errors 00000 v undefined invalid code 00001 v undefined invalid code 00010 v undefined invalid code 00011 v undefined invalid code 00101 v undefined invalid code 00110 v undefined invalid code 01000 v undefined invalid code 01100 v undefined invalid code 10000 v undefined invalid code 11001 v undefined invalid code table 12 look-up table for translating 5b symbols into 4b nibbles (cont?d) pcs code-group[4:0] name mii (txd/rxd)<3:0> interpretation
ADM7001/x data sheet function description data sheet 30 rev. 1.07, 2005-11-25 is entered, and the transmission and reception logic blocks become active. should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. carrier sense carrier sense (crs) for 100 mbits/s operation is asse rted upon the detection of two non contiguous zeros occurring within any 10-bit boundary of the received data stream. the carrier sense function is independe nt of symbol alignment. in switch mo de, crs is asserted during either packet transmission or reception. for repeater mode, crs is asserted only during packet reception. when the idle symbol pair is detected in the received data stream, crs is deasserted. in repeater mode, crs is only asserted due to receive activity. crs is intended to encapsulate rxdv. bad ssd detection a bad start of stream delimiter (bad ssd) is an error condit ion that occurs in the 100base-x receiver if carrier is detected (crs asserted) and a valid /j/k set of code-group (ssd) is not received. if this condition is detected, the ad m7001/x will assert rxer and present rxd[ 3:0] = 1110 to the internal mii for the cycles hat correspond to receive 5b code-groups until at least two idle code-groups are detected. once at least two idle code groups are detected, rxer and crs become deasserted. far-end fault auto negotiation provides a mechanism for transferring info rmation from the local station to the link partner that a remote fault has occurred for 100base-tx. as auto negotiati on is not currently specifi ed for operation over fiber, the far end fault indication functi on (fefi) provides this capab ility for 100base-fx applications. a remote fault is an error in the link that one station ca n detect while the other cannot. an example of this is a disconnected wire at a station?s transmitte r. this station will receive valid data and detect t hat the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propaga ting to the other station. a 100base-fx station that detects such a remote fault may modify its transmit ted idle stream from all ones to a group of 84 ones followed by a single 0. this is referred to as the fefi idle pattern. the fefi function is controlled by bit 3 of register 11 h . it is initialized to 1 (encoded ) if the selfx pin is at logic high level during power on reset. if th e fefi function is enabled the adm700 1/x will halt all curr ent operations and transmit the fefi idle pattern when fosd signal is de -asserted following a good link indication from the link integrity monitor. fosd signal is generated internally from the internal signal detect ci rcuit. transmission of the fefi idle pattern will continue until link up signal is asserted. if three or more fefi idle pa tterns are de tected by the ADM7001/x, bit 4 of the basic mo de status register (address 1h) is set to one until read by management. additionally, upon detection of far end fault, all re ceive and transmit mii acti vities are disabled/ignored. 3.1.3 100base-tx transmitter ADM7001/x implements a tp-pmd compliant transceiver for 100base-tx operation. the differential transmit driver is shared by the 10base-t and 100base-tx subsyst ems. this arrangement results in one device that uses the same external magnetics for both the 10base-t and the 100base-tx transmission with simple rc component connections. the individually wave-shaped 10base-t and 100base-tx transmit signals are multiplexed in the transmission output driver selection. ADM7001/x 100base-tx transmission driver implements mlt-3 translation and wave-shaping functions. the rise/fall time of the output signal is closely controlled to conform to the target range specified in the ansi tp-pmd standard. 3.1.4 100base-fx receiver signal is received through pecl receiver inputs from fiber tr ansceiver, and directly passed to clock recovery circuit for data/clock recovery. scrambler/de-scrambler is bypassed in 100base-fx.
data sheet 31 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description automatic ?signal_detect? function block when dis_anasden_n in regist er 18 is set to 0, ADM7001/x doesn't su pport sdp detection in fiber mode, which is used to connect to fiber transceiver to indicate there is signal on the fi ber. instead, adm70 01/x uses the data on rxp/rxn to detect consecutive 65 ?1? on the receive data (recovered from rxp/rxn) to determine whether ?signal? is detected or not. when the detect condition is tr ue (consecutive 65 bits ?1?), internal signal detect signal will be asserted to inform receiv e relative blocks to be ready for coming receive activities. 3.1.5 100base-fx transmitter in 100base fx transmit, the serial data stream is dr iven out as nrzi pecl signals, which enter fiber transceiver in differential-pairs form. fiber transceiver should be available working at 3.3 v environment. 3.1.6 10base-t module the 10base-t transceiver module is ieee 802.3 compliant. it includes th e receiver, transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link in tegrity functions, as defined in the standard. figure 4 provides an overview for the 10base-t module. the ADM7001/x 10base-t module is comprised of the following functional blocks: ? manchester encoder and decoder ? collision detector ? link test function ? transmit driver and receiver ? serial and parallel interface ? jabber and sqe test functions ? polarity detection and correction 3.1.7 operation modes the ADM7001/x 10base-t module is capable of operating in either half-duplex mode or full-duplex mode. in half- duplex mode, the ADM7001/x functions as an ieee 802.3 compliant transceiver with fully integrated filtering. the col signal is asserted during collisions or jabber events, and the crs signal is asserted during transmitting and receiving. in full duplex mode the ADM7001/x can simultaneously transmit and receive data. 3.1.8 manchester encoder/decoder data encoding and transmission begin when the transm ission enable input (txen) goes high and continues as long as the transceiver is in good link state. transmissi on ends when the transmission enable input goes low. the last transition occurs at the center of th e bit cell if the last bit is 1, or at the boundary of the bit cell if the last bit i s 0. a differential input receiver circuit accomplishes de coding and a phase-locked loop that separates the manchester-encoded data stream into clock signals and nrz data. the decoder detects the end of a frame when no more mid bit transitions are detected. within one and half bit times after the last bit, carrier sense is deasserted. 3.1.9 transmit driv er and receiver the ADM7001/x integrates all the required signal conditioni ng functions in its 10base-t block such that external filters are not required. only one isolation transfo rmer and impedance matching resistors are needed for the 10base-t transmit and receive interface. the internal transmit filtering ensures that all the harmonics in the transmission signal are attenuated properly. 3.1.10 smart squelch the smart squelch circuit is responsibl e for determining when valid data is pr esent on the differential receives. the ADM7001/x implements an intelligent receive squelch on the rxp/rxn differential inputs to ensure that impulse
ADM7001/x data sheet function description data sheet 32 rev. 1.07, 2005-11-25 noise on the receive inputs will not be mistaken for a valid signal. the squelch circuitr y employs a combination of amplitude and timing measurements (as specified in the ieee 802.3 10base-t standard) to determine the validity of data on the twisted-pair inputs. the "analog squelch circuit" checks th e signal at the start of the packet an d any pulses not exce eding the squelch level (either positive or negative, d epending upon polarity) will be rejected. once this first squelch level is overcome correctly, the oppo site squelch level must then be exceeded within 150ns. finally, the signal must exceed the original squelch level withi n an additional 150ns to ensure that the input wa veform will not be rejected. only after all these conditio ns have been satisfied will a control signal be generated to indica te to the remainder of the circuitry that valid data is present. figure 4 10base-t block diagram and data path valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end of packet. once good data has been detected, the squelch levels are reduced to minimize the effect of noise, causing premature end-of-packet detectio n. the receive squelch threshold level can be lowered for use in longer cable applications. this is ac hieved by setting bit 7 of register address 10 h . 3.1.11 carrier sense carrier sense (crs) is asserted due to receive activity on ce valid data is detected via the smart squelch function. for 10 mbit/s half duplex operation, crs is asserted duri ng either packet transmission or reception. for 10 mbit/s full duplex and repeater mode operations, the cr s is asserted only due to receive activity. 3.1.12 collision detection collision is detected internal to the mac, which is generated by an a nd function of txen and rxdv derived from internal timing recovery circuitry. no te should be taken that due to txen and rxdv are asynchronous to each other, col signal outputted by ADM7001/x is irrelevant to either txclk or rxclk.

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data sheet 33 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description 3.1.13 jabber function the jabber function monitors the ADM7001/x output and disa bles the transmitter if it attempts to transmit a longer than legal sized packet. if txen is high for greater than 24ms , the 10base-t transmitte r will be disabled. once disabled by the jabber function, the tran smitter stays disable for the entire time that the txen signal is asserted. this signal has to be de-asserted for approximately 408 ms (the un-jab time) before the jabber function re-enables the transmit outputs. the jabber function can be di sabled by programming bit 0 of register address 10 h to high. 3.1.14 link test function a link pulse is used to check the integrity of the connection with the remote end. if valid link pulses are not received, the link detector disables the 10base -t twisted-pair transmit ter, receiver, and collis ion detection functions. the link pulse generato r produces pulses as defined in ieee 802.3 10base-t st andard. each link pulse is nominally 100 ns in duration and is transmitted every 16 ms, in the absence of transmit data. setting bit 10 of register 10 h to high can disable link pulse check function. 3.1.15 automatic link polarity detection ADM7001/x's 10base-t transceiver module incorporates an ?automatic link polarity detection circuit?. the inverted polarity is determined when seven consecutive lin k pulses of inverted polarity or three consecutive packets are received with inverted end-of -packet pulses. if the input polarity is reversed, the error condition will be automatically corrected and reported in bit 13 of register 11 h . 3.1.16 clock synthesizer the ADM7001/x implements a clock synthesizer that ge nerates all the reference clocks needed from a single external frequency source. th e clock source must be a ttl level signal at 25 mhz 50ppm. 3.1.17 auto negotiation the auto negotiation function provides a mechanism fo r exchanging configuration information between two ends of a link segment and automatically selecting the highes t performance mode of oper ation supported by both devices. fast link pulse (flp) bursts provides the signaling used to co mmunicate auto ne gotiation abilities between two devices at each end of a link segment. for further detail regarding auto negotiation, refer to clause 28 of the ieee 802.3u specification. the ADM7001/x supports four different ethernet protocols, so the inclusion of auto negotiation ensures that the highest perfor mance protocol will be selected ba sed on the ability of the link partner. the auto negotiation function within the ADM7001/x can be co ntrolled either by internal register access or by the use of configuration pins ar e sampled. if disabled, auto negotiation will not occur until software enables bit 12 in register 0. if auto negotiation is enabled, the negotiation process will commence immediately. when auto negotiation is enabled, the ADM7001/x transmits the abilities programme d into the auto negotiation advertisement register at address 04 h via flp bursts. any combination of 10 mbps, 100 mbps, half duplex and full duplex modes may be selected. auto negotiation contro ls the exchange of configur ation information. upon successfully auto negotiation, the abilities reported by the link partner are stored in the auto negotiat ion link partner ability register at address 05 h . the contents of the ?aut o negotiation link partner ability register? are used to auto matically configur e to the highest performance protocol between the local and far-end nodes. software can determine which mode has been configured by auto negotiation by co mparing the contents of register 04 h and 05 h and then selecting the technology whose bit is set in both registers of highest priority relative to the following list. ? 100base-tx full duplex (highest priority) ? 100base-tx half duplex ? 10base-t full duplex
ADM7001/x data sheet function description data sheet 34 rev. 1.07, 2005-11-25 ? 10base-t half duplex (lowest priority) the basic mode control register at address 0 h provides control of enabling, disabling, and restarting of the auto negotiation function. when auto negotiati on is disabled, the speed selection bi t (bit 13) controls switching between 10 mbps or 100 mbps operation, while the duplex mode bi t (bit 8) controls switching between full duplex operation and half duplex operation. the speed selection and duple x mode bits have no effect on the mode of operation when the auto negotiation enable bit (bit 12) is set. the basic mode status register (bmsr) at address 1 h indicates the set of availabl e abilities for technology types (bit 15 to bit 11), auto negot iation ability (bit 3), and ex tended register capab ility (bit 0). these bits are hardwired to indicate the full functionality of the ADM7001/x. the bmsr also provides status on: ? whether auto negotiation is complete (bit 5) ? whether the link partner is advertising th at a remote fault has occurred (bit 4) ? whether a valid link has been established (bit 2) the auto negotiation advertis ement register at address 4 h indicates the auto negotiati on abilities to be advertised by the ADM7001/x. all available abilitie s are transmitted by default, but writin g to this register or configuring external pins can suppress any ability. the auto negotiation link partner ability register at address 05 h indicates the abilities of the link partner as indicated by auto negotiation communica tion. the contents of this register are considered valid when the auto negotiation complete bits (bit 5, register address 1 h and bit 4, register 17 h ) are set. 3.1.18 auto negotiation and speed configuration the twelve sets of four pins listed in table 13 configure the sp eed capability of each ch annel of ADM7001/x. the logic state of these pins is latched into t he advertisement register (register address 4 h ) for auto negotiation purpose. these pins are also used for evaluating the default value in the base mode control register (register 0 h ) according to table 13 channel configuration. 3.2 mac interface the ADM7001/x interfaces to 10/100 media access co ntrollers (mac) via the rmii, mii, or gpsi interface. 3.2.1 reduced media inde pendent interface (rmii) the reduced media independent interface (rmii) is compliant to the rmii consortium?s rmii rev. 1.2 specification. the refclk pin that supplies the 50 mhz reference cloc k to the ADM7001/x is used as the rmii refclk signal. all rmii signals with the exception of the assertion of crsdv_p are synchronous to refclk. see figure 5
data sheet 35 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description figure 5 rmii signal diagram 3.2.2 receive path for 100m figure 6 shows the relationship among refclk, crsdv, rxd an d rxer while receiving a valid packet. carrier sense is detected, which causes crsdv to assert asynch ronously to refclk. the received data is then placed into the fifo for resynchroni zation. after a minimum of 12 bits are plac ed into the fifo, the received data is presented onto rxd[ 1:0] synchronously to refclk. no te that while the fifo is f illing up rxd[1:0] is set to 00 until the first received di-bit of preamble (01) is presented onto rxd[1:0]. when carrier sense is de-asserted at the end of a packet, crsdv is de-asserted when the first di-bit of a nibble is presented onto rxd[1:0] synchronously to refclk. if there is still data in th e fifo that has not yet been presented onto rxd[1:0], then on the second di- bit of a nibble, crsdv reasserts. this pattern of assertio n and de-assertion continues until all received data in the fifo has been presented onto rxd[1:0]. rxer is in active for the duration of the received valid packet. figure 7 shows the relationship among refclk, crsdv and rxd[1:0] during a received false carrier event. crsdv is asserted asynchronously to refclk as in the va lid receive case shown in . however, once false carrier is detected, rxd[1:0] is changed to (10) (11) (value 1110 in mii) and rxer is asserted. both rxd[1:0] and rxer transition synchronously to refclk. after carrier sense is de-asserted, crsdv is de -asserted synchronously to refclk. figure 6 rmii reception without error refclk rxd crsdv 00 00 00 00 00 00 01 01 01 01 01 11 data data data data data data data data data 00 rxer carrier sense detected 00 00 preamble sfd carrier deasserted data
ADM7001/x data sheet function description data sheet 36 rev. 1.07, 2005-11-25 figure 7 rmii reception with false carrier (100m only) a receive symbol error event is shown in figure 8 . the packet with the symbol error is treated as if it were a valid packet with the exception that all di-bit s are substituted with the (01) pattern. figure 8 rmii reception with symbol error 3.2.3 receive path for 10m figure 9 10m rmii receive diagram in 10m mode, rxer will maintain low all the time due to false carrier an d symbol error is no t supported by 10m mode. different from 100m mode, rx d and crsdv can transit once per 10 refclk cycles. after carrier sense is de-asserted yet the fifo data is not fully presented onto rxd, the crsdv de-assertion and re-assertion also follow this rule. 3.2.4 transmit path for 100m figure 10 shows the relationship among refclk, txen an d txd[1:0] during a transmit event. txen and txd[1:0] are synchronous to refclk. when txen is assert ed, it indicates that txd[1:0] contains valid data to be transmitted. when txen is de-asserted, value on txd[1: 0] should be ignored. if an odd number of di-bits are presented onto txd[ 1:0] and txen, the final di-bit will be discarded by ADM7001/x.
data sheet 37 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description figure 10 100m rmii transmit diagram
ADM7001/x data sheet function description data sheet 38 rev. 1.07, 2005-11-25 3.2.5 transmit path for 10m in 10mbse-t mode, each di-bit must be repeated 10 times by the mac, txen and txd[1:0] should be synchronous to refclk. when txen is asserted, it indicates that data on txd[1:0] is valid for transmission. in 10base-t mode, it is possible that the number of pream ble bits and the number of frame bits received are not integer nibbles. the preamble is always padded up such that the sfd appears on the rmii aligned to the nibble boundary. extra bits at the end of the frame that do not complete a nibble are truncated by ad7001. figure 11 shows the timing diagram for 10m transmission. figure 11 10m rmii transmit diagram 3.2.6 media independ ent interface (mii) signal diagram for mii in terface is shown in figure 12 . table 13 channel configuration recommend value auto negotiation capability anendis rec_10m tp_full duplex enable disable 100 full 100 half 10 full 10 half 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
data sheet 39 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description figure 12 mii signal diagram 3.2.7 receive path for mii figure 13 shows the relationship among rxclk, rxdv, rxd and crs during a reception of valid packet. carrier sense is detected and asserted asynchronously to rx clk by ADM7001/x. when ADM7001/x detects there is valid data, rxdv and the received data are presented onto rx d[3:0] synchronously to rx_clk. whenever received data is not valid anymore, rxdv will be de-asserted by ad m7001/x and "0" will be put on rxd[3:0]. figure 13 mii receive without error figure 14 shows the relationship among rxclk, rxdv and rxd[ 3:0] during a received false carrier event. crs is asserted asynchronously to rxclk as in the valid receive case shown in figure 15 . however, once false carrier is detected, rxd[3:0] is changed to (1110) and rxer is asserted. both rxd[3:0] and rxer transit synchronously to rxclk.
ADM7001/x data sheet function description data sheet 40 rev. 1.07, 2005-11-25 figure 14 mii receive with false carrier a receive symbol error event is shown in figure 15 . the packet with the symbol error is treated as if it were a valid packet with the exception that all bits are substituted wit h the (0101) pattern. rxer will keep low in 10m operation. figure 15 mii receive with symb ol error(100m only)
data sheet 41 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description 3.2.8 transmit path for mii figure 16 shows the relationship among txclk, txen and txd[3:0] during a transm it event. txen and txd[3:0] are synchronous to txclk, which is generated by mac. txclk is running at 25m in 100m mode and 2.5m in 10m mode. when txen is asserted, it indicates that txd[3:0] contains valid da ta to be transmitted. when txen is de-asserted, value on txd[1:0] should be ignored. figure 16 mii transmission when ADM7001/x operates in half dupl ex mode, either 10m or 100m, it will assert col si gnal whenever it detects there is collision on the medium. figure 17 shows the timing di agram for mii collision. figure 17 mii transmit with collision (half duplex only) 3.2.9 general purpose serial interface (gpsi) signal diagram for mii in terface is shown in figure 18 .
ADM7001/x data sheet function description data sheet 42 rev. 1.07, 2005-11-25 figure 18 gpsi signal diagram 3.2.10 receive path for gpsi figure 19 shows the relationship among rxclk, rxd and crs during a receive of valid packet. carrier sense is detected and asserted asynchronously to rxclk by ad m7001/x. when ADM7001/x detects there is valid data, received data is presented onto rxd synchronously to rxclk. whenever received data is not valid anymore, crs will be de-asserted by adm700 1/x and "0" will be put on rxd. figure 19 gpsi receive diagram 3.2.11 transmit path for gpsi figure 20 shows the relationship among txclk, txen and txd during a transmit event. txen and txd are synchronous to txclk, which is generated by mac. tx clk is running at 10m in 10m mode. when txen is asserted, it indicates that txd contains valid data to be transmitted. when txen is de-asserted, value on txd should be ignored.
data sheet 43 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description figure 20 gpsi transmit diagram 3.3 led display register 19 is used for different mode led display. adm7 001/x provides power on led self test to minimize and ease the system test cost. all leds will be off during power on reset (output value same as recommend value on led pins). after power on reset, all internal pa rallel leds will be on for 2 seco nds to ease manuf acture overhead there are three types of led supported by ADM7001/x internally. the first is lnkact, which represents the status of link and transmit/receive activity, the second is ldspd, which indicates the speed status, and the last is dupcol, which shows pure duplex st atus in full duplex and duplex/collisi on combined status in half duplex. all these three led can be controlled by re gister 19 to change display contents. after led self test, table 14 , table 15 , table 16 show the on/off polarity according to different recommended value setting for ldspd, dupcol an d lnkact. when the recommend valu e is high, ADM7001/x will drive led low; ADM7001/x will drive the led high wh en the recommend value is low, instead. besides duplex, speed, link and activity status, ADM7001/x also provides cable information that can be shown on leds when register 19 is programmed to distance led display (see table 17 ) table 14 speed led display speed spdled 10m 0 100m 1 link fail 1 table 15 duplex led display duplex dupcol half full link up blink (high) when collision low all the time link fail high all the time high all the time table 16 activity/link led display speed link/activity link activity link up low blink (high) when rx/tx link fail high all the time high all the time
ADM7001/x data sheet function description data sheet 44 rev. 1.07, 2005-11-25 3.4 management register access the smi consists of two pins, management data clock (mdc) and management data input/output (mdio). the ADM7001/x is designed to support an mdc frequency s pecified in the ieee specificat ion of up to 2.5 mhz. the mdio line is bi-directional and may be shared by up to 32 devices. the mdio pin requires a 1.5 k ? pull-up which, during idle and turnaround periods, will pull mdio to a logic one state. each mii management data frame is 64 bits long. th e first 32 bits are preamble consisting of 32 contiguous logic one bits on mdio and 32 corres ponding cycles on mdc. following prea mble is the start-of-frame field indicated by a <01> pattern. the next field signals the operation code (op): <10> indicates read from mii management register operation, and <01> indicates writ e to mii management register operation. the next two fields are phy device address and mii management register address. both of them are 5 bits wide and the most significant bit is transferred first. during read operation, a 2-bit turn around (ta) time s pacing between the register addr ess field and data field is provided for the mdio to avoid contention. following the turnaround time, a 16-bit data stream is read from or written into the mii management registers of the ADM7001/x 3.4.1 preamble suppression the ADM7001/x supports a preamble suppression mode as i ndicated by an 1 in bit 6 of the basic mode status register (register 1h). if the station management entity (i.e. mac or other management controller) determines that all phys in the system support preamble suppression by read ing a 1 in this bit, then the station management entity needs not to generate preamble for each management trans action. the ADM7001/x requir es a single initialization sequence of 32 bits of preamble fo llowing powerup/hardwar e reset. this requirement is generally met by pulling- up the resistor of mdio. while the ADM7001/x will respon d to management accesse s without preamble, a minimum of one idle bit between management transactions is required as specified in ieee 802.3u. when ADM7001/x detects that there is physical ad dress match, then it will ena ble read/write capability for external access. when neither physical address nor register address is matc hed, then ADM7001/x will tristate the mdio pin. figure 21 smii read operation 3.4.2 reset operation the ADM7001/x can be reset either by hardware or software. a hardware reset is accomplished by applying a negative pulse, with duration of at le ast 200 ms to the rc pin of the ADM7001/x during normal operation to table 17 cable distance led display lnkact dupcol ledspd cable distance 1 1 0 0 to 40 meters 1 0 0 40 to 80 meters 0 0 0 80 to 120 meters 1 1 1 reserved
data sheet 45 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description guarantee internal power on reset circuit is reset well. setting the reset bit in the basic mode control activates software reset register (bit 15, register 0 h ). this bit is self-clearing and , when set, will return a value of 1 until the software reset operation has completed, please no te that internal sram will not be reset during software reset. figure 22 smii write operation hardware reset operation samples the pins and initializes a ll registers to their default values. this process includes re-evaluation of all hardware configurable registers. a software reset will reset an individual phy and it does not latch the external pins nor rese t the registers to their respective default value. logic levels on several i/o pins are detected during a hardware reset to determine the initial functionality of ADM7001/x. some of these pins are used as output ports after reset operation. care must be taken to ensure that the configuration setup will not interfere with norma l operation. dedicated configuration pins can be tied to vcc or ground directly. configuration pins multiple xed with logic level output functions should be either weakly pulled up or weakly pulled down through resistors. 3.5 power management an analog block is designed for carrier sense detectin g. when there is no carrier sense presented on medium (cable not attached), then "signal detect" will not be on. whenev er cable is attached to ADM7001/x and the voltage threshold is above +/ - 50mv, then sd will be asserted high to in dicate that there is cable attached to ADM7001/x. all internal blocks e xcept management block will be disabled (reset) before sd is asserted. when sd is asserted, internal auto negotiation block will be turned on a nd the 10m transmit driver will also be turned on for auto negotiat ion process. auto negotiation will issue contro l signals to control 10m receive and 100m a/d block according to different state in arbitration block diagram. during auto negotiation, all digital blocks except management and link monitor blocks will be disabled to reduce power consumption. whenever operating speed is determined (either auto negotiation is on or off), the non-active speed relative circuit will be disabled all the time to save more power. for exam ple, when correspo nding port is oper ating on 10m, then 100m relative blocks will be disa bled and 10m relative blocks will be disabled whenever co rresponding port is in 100m mode. auto n egotiation block will be reset when sd signal goes from hi gh to low. see figure 23 for the state diagram for this algorithm.
ADM7001/x data sheet function description data sheet 46 rev. 1.07, 2005-11-25 figure 23 medium detect power management flow chart another way to reduce instan t power is to separate the le d display period. all 4 leds will be divided into 4 time frame and each time frame occupies 1 us. one and only one led will be driv en at each time frame to reduce instant current consumed from led. 3.6 voltage regulator ADM7001/x requires two different levels, 3.3 v and 2.5 v, of voltage supply to provide the power to different parts of circuitry inside the chip. ADM7001/x has a build -in voltage regulator circuitry to generate the 2.5 v voltage (vcc25out) from 3.3 v power source (vcc3in). external application circuitry is shown in figure 24 .
data sheet 47 rev. 1.07, 2005-11-25 ADM7001/x data sheet function description figure 24 power and ground filtering vcco_25 gndik rxdv/crsdv/dis_amdix rmii_en/rx_clk isolate/rxer gndo vccik_25 txer txclk txen txd0 txd1 pwrdown_n anen/colled dupful/dupled spd100/spdled fefi_en/lnkact phyad0/intr vcco_2.5 gndo conv/repeater/crs col/gpsi txd3 txd2 ADM7001 qfp 48 gndik test1 xo xi vcc33in reset_n mdio mdc phyad1/rxd3 phyad2/rxd2 pyyad3/rxd1 phyad4/rxd0 vcc25out(core) txp txn gndpll vccpll_25 rtx test0 gndtr sd/fxen rxp rxn vcca_25 ?? ?? ?? ? ? ? ? ? ?? ?? ?? ?? ?? ?? ? ? ? ? ?? ?? ?? ?? ?? ? ? ?? ?? ? ?? ? ? ? ? ?? ? ?? ?? ?? ?? ?? ? ? ? ?? ? ?? ??? ?? ??? ?? ??? ?? ?? ?? ?? ?? ? ?? ? ? ?? ?? ? ? ?? ? ??? ? ??? ? ??? ?? ????? ? ??? ?? ??? ??? ? ? ??? ?? ??
ADM7001/x data sheet registers description data sheet 48 rev. 1.07, 2005-11-25 4 registers description the register is addressed wordwise. table 18 registers address space module base address end address note phy 00 h 1f h table 19 registers overview register short name register long name offset address page number cr control register 00 h 50 sr status register 01 h 52 phy_ir0 phy identifier register 0 02 h 55 phy_ir1 phy identifier register 1 03 h 55 advertisement auto negotiation advertisement register 04 h 56 anlpa auto negotiation li nk partner ability 05 h 57 aner auto negotiation expansion register 06 h 58 res0 reserved 0 07 h 59 gpcr generic phy control/configuration register 10 h 60 p10_mcr phy 10m module configuration register 11 h 62 p100_mcr phy 100m module control register 12 h 64 lcr led configuration register 13 h 65 ier interrupt enable register 14 h 67 pgsr phy generic status register 16 h 68 pssr phy specific status register 17 h 69 prvsr phy recommend value status register 18 h 70 isr interrupt status register 19 h 71 recr receive error counter register 1d h 72 cir chip id register 1f h 73 table 20 registers access types mode symbol description hardware (hw) description software (sw) read/write rw register is used as input for the hw register is read and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) write w register is writable by sw read/write hardware affected rwh register can be modified by hw register can be modified by hw, but the priority sw versus hw has to be specified rwv
data sheet 49 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description 4.1 register description read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latch high signal at high level, clear on read sw can read the register latch low, self clearing llsc latch high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latch high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) latch low, mask clearing llmk latch high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) interrupt high, self clearing ihsc differentiate the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiate the in put signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiate the in put signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiate the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interr upt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is read and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be clea red due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is read and writable by sw. table 21 registers clock domains clock short name description table 20 registers access types (cont?d) mode symbol description hardware (hw) description software (sw)
ADM7001/x data sheet registers description data sheet 50 rev. 1.07, 2005-11-25 control register cr offset reset value control register 00 h 3000 h field bits type description rst 15 rwsc reset setting this bit initiates th e software reset function that resets the selected port, except for the phase-locked loop circuit. it will re-latch in all hardware configuration pin values. the software reset process takes 25us to complete. this bit, which is se lf-clearing, returns a value of 1 until the reset process is complete. 0 b rst_0 , normal operation 1 b rst_1 , phy reset lpbk 14 rw back enable this bit controls the phy loop back operation that isolates the network transmitter outputs (txp and txn) and routes the mii transmit data to the mii receive data path. this function should only be used when auto negotiation is disabled (bit12 = 0) . the specific phy (10base-t or 100base-x) used for this operation is determined by bits 12 and 13. 0 b lpbk_0 , disable loop back mode 1 b lpbk_1 , enable loop back mode ssl 13 rw speed selection lsb speed_lsb 0.60.13 link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in which case, t he value of this bit is ignored). 00 b 10m , 10 mbit/s 01 b 100m , 100 mbit/s 10 b 1000m , 1000 mbit/s 11 b res , reserved anen 12 rw auto negotiation enable this bit determines whether the link speed should set up by the auto negotiation process or not. it is se t at power up or reset if the pi_recanen pin detects a logic 1 in put level in twisted-pair mode. 0 b anen_0 , disable auto negotiation process 1 b anen_1 , enable auto negotiation process uzvf 567 uz /3%. uz 66/ uz $1(1 uz 3'1 uz ,62 uzvf 5$1 uz '3/; uz &7 ur 660 ur 5hv
data sheet 51 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description pdn 11 rw power down enable ored result with pi_pwrdn pin. setting this bit high or asserting the pi_pwrdn puts the phy841f into power down mode. during the power down mode, txp/txn and all led output s are tristated and the mii/rmii interfaces are isolated. 0 b pdn_0 , normal operation 1 b pdn_1 , power down iso 10 rw isolate phy841f from network setting this control bit isolates the part from the rmii/mii, with the exception of the serial management inte rface. when this bit is asserted, the phy841f does not respond to tx d, txen and txer inputs, and it presents a high impedance on its txc, rxc, crsdv, rxer, rxd, col and crs outputs. 0 b iso_0 , normal operation 1 b iso_1 , isolate phy from mii/rmii ran 9 rwsc restart auto negotiation anen_rst. setting this bit while auto negotiation is enabled forces a new auto negotiation process to start. this bit is self-clearing and returns to 0 after the auto negotiation process has commenced. 0 b ran_0 , normal operation 1 b ran_1 , restart auto negotiation process dplx 8 rw duplex mode if auto negotiation is disabled, this bit determines the duplex mode for the link. 0 b dplx_0 , half duplex mode 1 b dplx_1 , full duplex mode ct 7 rw collision test when set, this bit will cause the col si gnal of mii interf ace to be asserted in response to the assertion of txen. 0 b ct_0 , disable col signal test 1 b ct_1 , enable col signal test ssm 6 ro speed selection msb speed_msb. set to 0 all the time in dicate that the phy841f does not support 1000 mbit/s function. res 5:0 ro reserved not applicable field bits type description
ADM7001/x data sheet registers description data sheet 52 rev. 1.07, 2005-11-25 status register sr offset reset value status register 01 h 7849 h ur 7 ur 7;) ur 7;+ ur 7) ur 7+ ur 7 ur 5hv ur 6835 ur $1b& ur 5)' ur $1(* uroo /,1. urok -$% ur ;71'
data sheet 53 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description field bits type description t4 15 ro 100base-t4 capable set to 0 all the time to indicate that the phy841f does not support 100base-t4. txf 14 100base-x full duplex capable set to 1 all the time to indicate that the phy841f does support full duplex mode. txh 13 100base-x half duplex capable set to 1 all the time to indicate that the phy841f does support half duplex mode tf 12 10m full duplex capable tp: set to 1 all the time to indicate that the phy841f does support 10m full duplex mode. fx: set to 0 all the time to indicate that the phy841f does not support 10m full duplex mode th 11 10m half duplex capable tp: set to 1 all the time to indicate that the phy841f does support 10m half duplex mode. fx: set to 0 all the time to indicate that the phy841f does not support 10m half duplex mode t2 10 100base-t2 capable set to 0 all the time to indicate that the phy841f does not support 100base-t2. res 9:7 reserved not applicable supr 6 mf preamble suppression capable this bit is hardwired to 1 indicating that the phy841f accepts management frame without preamble. minimum 32 preamble bits are required following power-on or hardware reset. one idle bit is required between any two management tran sactions as per ieee 802.3u specification. an_c 5 auto negotiation complete if auto negotiation is enabled, th is bit indicates whether the auto negotiation process has been completed or not. set to 0 all the time when fiber mode is selected. 0 b an_c_0 , auto negotiation process not completed 1 b an_c_1 , auto negotiation process completed
ADM7001/x data sheet registers description data sheet 54 rev. 1.07, 2005-11-25 rfd 4 ro remote fault detect this bit is latched to 1 if the rf bit in the auto negotiation link partner ability register (bit 13, r egister address 05h) is se t or the receive channel meets the far end fault indication function criteria. it is unlatched when this register is read. 0 b rfd_0 , remote faul t not detected 1 b rfd_1 , remote fault detected aneg 3 auto negotiation ability tp: this bit is set to 1 all the time, indicating that phy8 41f is capable of auto negotiation. fx: this bit is set to 0 all the time, indicating that phy841f is not capable of auto negotiation in fiber mode. 0 b aneg_0 , not capable of auto negotiation 1 b aneg_1 , capable of auto negotiation link 2 ro, llsc link status this bit reflects the curr ent state of the link -test- fail state machine. loss of a valid link causes a 0 latched into th is bit. it remains 0 until this register is read by the serial management interface. whenever linkup, this bit should be read twice to get link up status 0 b link_0 , link is down 1 b link_1 , link is up jab 1 ro, lhsc jabber detect 0 b jab_0 , jabber condition not detected 1 b jab_1 , jabber condition detected xtnd 0 ro extended capability this bit defaults to 1, indicating that the phy841f implements extended registers. 0 b xtnd_0 , no extended register set 1 b xtnd_1 , extended register set field bits type description
data sheet 55 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description phy identifier phy identifier register 1 phy_ir0 offset reset value phy identifier register 0 02 h 002e h field bits type description phyid 15:0 ro phy-id ieee address phy_ir1 offset reset value phy identifier register 1 03 h cc62 h field bits type description phyid 15:10 ro phy-id 15:0 ieee address/model no./rev. no. model 9:4 model 5:0 admtek phy revision id. revid 3:0 rev-id 3:0 admtek phy revision id. ur 3+<,' ur 3+<,' ur 02'(/ ur 5(9,'
ADM7001/x data sheet registers description data sheet 56 rev. 1.07, 2005-11-25 advertisement advertisement offset reset value auto negotiation advertisement register 04 h 01e1 h field bits type description np 15 rw next page this bit is defaults to 1, indicati ng that phy841f is next page capable. res 14 ro reserved not applicable rf 13 rw remote fault this bit is written by serial mana gement interface for the purpose of communicating the remote fault condi tion to the auto negotiation link partner. 0 b nrfd , no remote fault has been detected 1 b rfd , remote fault has been detected res 12 ro reserved not applicable apd 11 rw asymmetric pa use direction bit[11:10] capability 00 b np , no pause 01 b sp , symmetric pause 10 b ap , asymmetric pause toward link partner 11 b bsp , both symmetric pause and asymmetric pause toward local device pse 10 rw pause operation for full duplex value on paurec will be stored in this bit during power on reset. t4 9 ro technology ability for 100base-t4 defaults to 0. uz 13 ur 5hv uz 5) ur 5hv uz $3' uz 36( ur 7 uz 7;) uz 7;' uz 7) uz 7' ur 6ho
data sheet 57 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description auto negotiation link partner ability txf 8 rw 100base-tx full duplex 0 b ncfdo , not capable of 100m full duplex operation 1 b cfdo , capable of 100m full duplex operation txd 7 100base-tx half duplex 0 b txd_0 , not capable of 100m operation 1 b txd_1 , capable of 100m operation tf 6 10base-t full duplex 0 b tf_0 , not capable of 10m full duplex operation 1 b tf_1 , capable of 10m full duplex operation td 5 10base-t half duplex 0 b td_0 , not capable of 10m operation 1 b td_1 , capable of 10m operation sel 4:0 ro selector field these 5 bits are hardwired to 00001 b , indicating that the phy841f supports ieee 802 .3 csma/cd. anlpa offset reset value auto negotiation link partner ability 05 h 01e1 h field bits type description ur 13* ur $&. ur 5) ur 5hv ur /3$3 ur /33 ur /37$ ur 7;) ur 7;' ur 7) ur 7' ur 6ho
ADM7001/x data sheet registers description data sheet 58 rev. 1.07, 2005-11-25 auto negotiation expansion register field bits type description npg 15 ro next page 0 b npg_0 , not capable of next page function 1 b npg_1 , capable of next page function ack 14 acknowledge 0 b ack_0 , not acknowledged 1 b ack_1 , link partner acknowledges reception of t he ability data word rf 13 remote fault 0 b rf_0 , no remote fault has been detected 1 b rf_1 , remote fault has been detected res 12 reserved not applicable lpap 11 link partner asymmetric pause direction lpp 10 link partner pause capability value on paurec will be stored in this bit during power on reset. lpta 9 link partner technology ability for 100base-t4 defaults to 0. txf 8 100base-tx full duplex 0 b txf_0 , not capable of 100m full duplex operation 1 b txf_1 , capable of 100m full duplex operation txd 7 100base-tx half duplex 1 b txd_1 , capable of 100m operation 0 b txd_2 , not capable of 100m operation tf 6 10base-t full duplex 1 b tf_1 , capable of 10m full duplex operation 0 b tf_0 , not capable of 10m full duplex operation td 5 10base-t half duplex 1 b td_1 , capable of 10m operation 0 b td_0 , not capable of 10m operation sel 4:0 encoding definitions aner offset reset value auto negotiation expansion register 06 h 0000 h ur 5hv urok 3)/7 ur /313 ur 1;3* urok 35&9 ur /3$1
data sheet 59 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description reserved 0 field bits type description res 15:5 ro reserved not applicable pflt 4 ro, lhsc parallel detection fault 0 b pflt_0 , no fault detect 1 b pflt_1 , fault has been detected lpnp 3 ro link partner next page able 0 b lpnp_0 , link partner is not next page capable 1 b lpnp_1 , link partner is next page capable nxpg 2 next page able 1 b nxpg_1 , next page enable. 0 b nxpg_0 , next page disable prcv 1 ro, lhsc page received 0 b prcv_0 , no new page has been received 1 b prcv_1 , a new page has been received lpan 0 ro link partner auto negotiation able 0 b lpan_0 , link partner is not auto negotiable 1 b lpan_1 , link partner is auto negotiable res0 offset reset value reserved 0 07 h reserved h field bits type description res 15:0 ro reserved not applicable table 22 reserved registers register short name register long name offset address res1 reserved 1 08 h res2 reserved 2 09 h res3 reserved 3 0a h res4 reserved 4 0b h res5 reserved 5 0c h res6 reserved 6 0d h ur 5hv
ADM7001/x data sheet registers description data sheet 60 rev. 1.07, 2005-11-25 generic phy control/configuration register note: phy control/configuration registers start from address 16 to 21. res7 reserved 7 0e h res8 reserved 8 0f h res9 reserved 9 15 h res10 reserved 10 1a h res11 reserved 11 1b h res12 reserved 12 1c h res 13 reserved 13 1e h gpcr offset reset value generic phy control/configuration register 10 h 1000 h field bits type description ifsel 15:14 ro interface select. value on rmii_en and gpsi will be st ored in ifsel[1] and ifsel[0], respectively 00 b , mii 01 b , gpsi 1x b , rmii lbkmd 13:12 rw loop back mode select. when 0.14 lpbk is set to 1, these two bits are set to 01 by default. value on these two bits can be modified through mdc/mdio. when 0.14 lpbk is set to 0, these two bits are reset to 00 and can't be updated by mdc/mdio. note: both 10m and 100m loopback should be covered by ad2106. 00 b , disable loop back 01 b , pcs layer loop back mode 10 b , pma layer loop back mode 11 b , pmd layer loop back mode res 11:10 ro reserved not applicable flt 9 rw enable called output remote fault status 0 b flt_0 , disable. 1 b flt_1 , enable. table 22 reserved registers (cont?d) register short name register long name offset address ur ,)6(/ uz /%.0' ur 5hv uz )/7 uz &rqy ur 5hv uz ;29( 1 uz 5hv uz (q uz '30*
data sheet 61 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description conv 8 rw converter mode (only valid in rmii mode) 0 b conv_0 , normal mode 1 b conv_1 , converter mode res 7:5 ro reserved not applicable xoven 4 rw cross over auto detect enable 0 b xoven_0 , disable. 1 b xoven_1 , enable. res 3:2 rw admtek reserved bits. writing value other than 0 to these two bits may cause abnormal operation. en8 1 rw enable register 8 to store next page information. 0 b en8_0 , store next page in register 5. 1 b en8_1 , store next page in register 8 dpmg 0 rw disable power management feature 0 b dpmg_0 , enable. enable medium detect function. 1 b dpmg_1 , disable. medium_on is high all the time. field bits type description
ADM7001/x data sheet registers description data sheet 62 rev. 1.07, 2005-11-25 phy 10m module configuration register p10_mcr offset reset value phy 10m module configuration register 11 h 0008 h field bits type description res 15 ro reserved not applicable ur 5hv uz 606 uz 5hv uz 5hv uz ,7&( uz 5hv uz 5hv uz 5hv uz $3' uz 5-0 uz 7-' uz 17+ uz )5/
data sheet 63 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description sms 14 rw 10base-t serial mode select. only available when ad2106 works in 10m mode. 0 b sms_0 , 10m mii or rmii mode (according to rmii_en) 1 b sms_1 , 10m serial mode (seven wire mode) res 13 admtek reserved bits. writing value other than 1 to this bit may cause abnormal operation. res 12:11 admtek reserved bits. writing value other than 0 to these two bits may cause abnormal operation. itce 10 polarity interval timer check enable. 0 b itce_0 , disable 1 b itce_1 , enable res 9 admtek reserved bits. writing value other than 1 to this bit may cause abnormal operation. res 8:6 admtek reserved bits. writing value other than 5 to these three bits may cause abnormal operation. res 5 admtek reserved bits. writing value other than 1 to this bit may cause abnormal operation. apd 4 auto polarity disable 0 b apd_0 , normal 1 b apd_1 , disable rjm 3 enable receive jabber monitor 0 b rjm_0 , disable 1 b rjm_1 , enable tjd 2 disable transmit jabber 0 b tjd_0 , enable transmit jabber function 1 b tjd_1 , disable transmit jabber function nth 1 normal threshold 0 b nth_0 , lower 10base-t re ceive threshold 1 b nth_1 , normal 10base-t receive threshold frl 0 force 10m receive good link. 0 b frl_0 , normal operation 1 b frl_1 , force good link field bits type description
ADM7001/x data sheet registers description data sheet 64 rev. 1.07, 2005-11-25 phy 100m module control register p100_mcr offset reset value phy 100m module control register 12 h 0022 h field bits type description res 15:12 ro reserved not applicable res 11:10 rw admtek reserved bits. writing value other than 0 to these two bits may cause abnormal operation. res 9:8 admtek reserved bits. writing value other than 0 to these two bits may cause abnormal operation. fxsel 7 fiber select. 0 b selfx_0 , tp mode 1 b selfx_1 , fiber mode res 6:5 admtek reserved bits. writing value other than 0 to these two bits may cause abnormal operation. scr 4 disable scrambler when set to fiber mode, this bit will be forced to 1 automatically. write 0 to this bit in fiber mode has no effect. 0 b scr_0 , enable 1 b scr_1 , disable fefi 3 enable fefi 0 b fefi_0 , disable 1 b fefi_1 , enable cle 2 ro disable cable length led indication when this bit is set to 0, spdled, colled and lnkactled are used to represent twisted pair cable length. see spdled description for more detail 0 b cle_0 , enable cable length led 1 b cle_1 , disable cable length led iac 1 rw interrupt active value control 0 b iac_0 , active low 1 b iac_1 , active high res 0 admtek reserved bits. writing value other than 0 to this bit may cause abnormal operation. ur 5hv uz 5hv uz 5hv uz )[6h o uz 5hv uz 6&5 uz )(), ur &/( uz ,$& uz 5hv
data sheet 65 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description led configuration register lcr offset reset value led configuration register 13 h 0a34 h field bits type description res 15:12 ro reserved not applicable lnkctrl 11:8 ro link/act led control 0000 b , collision 0001 b , all errors 0010 b , duplex 0011 b , duplex/collision 0100 b , speed 0101 b , link 0110 b , transmit activity 0111 b , receive activity 1000 b , tx/rx activity 1001 b , link/receive activity 1010 b , link and tx/rx activity 1011 b , 100m false carrier error/10m receive jabber 1100 b , 100m error end of stream/10m transmit jabber 1101 b , reserved 1110 b , distance (see led description for more detail) colctrl 7:4 ro collision led control 0000 b , collision 0001 b , all errors 0010 b , duplex 0011 b , duplex/collision 0100 b , speed 0101 b , link 0110 b , transmit activity 0111 b , receive activity 1000 b , tx/rx activity 1001 b , link/receive activity 1010 b , link and tx/rx activity 1011 b , 100m false carrier error/10m receive jabber 1100 b , 100m error end of stream/10m transmit jabber 1101 b , reserved 1110 b , distance (see led description for more detail) ur 5hv ur /1.&75/ ur &2/&75/ ur 63'&75/
ADM7001/x data sheet registers description data sheet 66 rev. 1.07, 2005-11-25 spdctrl 3:0 ro speed led control 0000 b , collision 0001 b , all errors 0010 b , duplex 0011 b , duplex/collision 0100 b , speed 0101 b , link 0110 b , transmit activity 0111 b , receive activity 1000 b , tx/rx activity 1001 b , link/receive activity 1010 b , link and tx/rx activity 1011 b , 100m false carrier error/10m receive jabber 1100 b , 100m error end of stream/10m transmit jabber 1101 b , reserved 1110 b , distance (see led description for more detail) field bits type description
data sheet 67 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description interrupt enable register ier offset reset value interrupt enable register 14 h 03ff h field bits type description res 15:10 ro reserved not applicable xchg 9 rw cross over mode changed interrupt enable 0 b xchg_0 , interrupt disable 1 b xchg_1 , interrupt enable scie 8 speed changed interrupt enable 0 b scie_0 , interrupt disable 1 b scie_1 , interrupt enable dcie 7 duplex changed interrupt enable 0 b dcie_0 , interrupt disable 1 b dcie_1 , interrupt enable prie 6 page received interrupt enable 0 b prie_0 , interrupt disable 1 b prie_1 , interrupt enable lsce 5 link status changed interrupt enable 0 b lsce_0 , interrupt disable 1 b lsce_1 , interrupt enable seie 4 symbol error interrupt enable 0 b seie_0 , interrupt disable 1 b seie_1 , interrupt enable fcar 3 false carrier in terrupt enable 0 b fcar_0 , interrupt disable 1 b fcar_1 , interrupt enable tjie 2 transmit jabber interrupt enable 0 b tjie_0 , interrupt disable 1 b tjie_1 , interrupt enable rjie 1 receive jabber interrupt enable 0 b rjie_0 , interrupt disable 1 b rjie_1 , interrupt enable eese 0 error end of stream enable 0 b eese_0 , interrupt disable 1 b eese_1 , interrupt enable ur 5hv uz ;&+* uz 6&,( uz '&,( uz 35,( uz /6&( uz 6(,( uz )&$5 uz 7-,( uz 5-,( uz ((6(
ADM7001/x data sheet registers description data sheet 68 rev. 1.07, 2005-11-25 phy generic status register note: phy status registers start from 22 to 28 (29 to 30 reserves for further use) pgsr offset reset value phy generic status register 16 h 0000 h field bits type description res 15:14 ro reserved not applicable res 13:11 reserved not applicable md 10 medium detect real time status for medium detect signal. 0 b md_0 , medium_detect fail 1 b md_1 , medium_detect pass fxen 9 fiber enable only changed when phy reset. or?ed result of pi_selfx and 17.9 (selfx) 0 b fxen_0 , tx mode 1 b fxen_1 , fx mode xover 8 cross over status 0 b xovs_0 , mdi mode 1 b xovs_1 , mdix mode cblen 7:0 cable length. only valid for 100m msb is ic0 1a h , 40 meters 22 h , 60 meters 94 h , 80 meters 9a h , 100 meters a2 h , 120 meters ab h , 140 meters ur 5hv ur 5hv ur 0' ur );(1 ur ;29( 5 ur &%/(1
data sheet 69 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description phy specific st atus register pssr offset reset value phy specific st atus register 17 h 0060 h field bits type description res 15:12 ro reserved not applicable jrx 11 real time 10m receive jabber status 0 b jrx_0 , no jabber 1 b jrx_1 , jabber jtx 10 real time 10m transmit jabber status 0 b jtx_0 , no jabber 1 b jtx_1 , jabber pol 9 polarity only available in 10m. 0 b pol_0 , normal polarity 1 b pol_1 , polarity reversed pout 8 pause out capability disabled when half duplex. 0 b pout_0 , lack of paus e out capability 1 b pout_1 , has pause out capability pin 7 pause in capability disabled when half duplex. 0 b pin_0 , has pause in capability 1 b pin_1 , lack of pause in capability dup 6 operating duplex 0 b dup_0 , half duplex 1 b dup_1 , full duplex spd 5 operating speed 0 b spd_0 , 10mb/s 1 b spd_1 , 100mb/s link 4 real time link status 0 b link_0 , link down 1 b link_1 , link up rpau 3 pause recommend value only changed when phy reset. this bit is disabled automatically when rdup is 0. 0 b rpau_0 , pause disable 1 b rpau_1 , pause enable ur 5hv ur -5; ur -7; ur 32/ ur 3287 ur 3,1 ur '83 ur 63' ur /,1. ur 53$8 ur 5'83 ur 563' ur 5$19
ADM7001/x data sheet registers description data sheet 70 rev. 1.07, 2005-11-25 phy recommend value status register rdup 2 ro duplex recommended value only changed when phy reset. 0 b rdup_0 , half duplex 1 b rdup_1 , full duplex rspd 1 speed recommend value only changed when phy reset. 0 b rspd_0 , 10m 1 b rspd_1 , 100m ranv 0 recommended auto negotiation value only changed when phy reset. prvsr offset reset value phy recommend value status register 18 h 0000 h field bits type description res 15 ro reserved not applicable ranv 14 auto negotiation recommend value fsel 13 fiber select recommend value rspd 12 speed recommend value 0 b rspd_1 , 10m 1 b rspd_0 , 100m rdup 11 duplex recommend value 0 b rdup_0 , half duplex 1 b rdup_1 , full duplex prec 10 pause capability recommend value 0 b prec_0 , pause disable 1 b prec_1 , pause enable fefd 9 far end fault disable 0 b fefd_0 , enable 1 b fefd_1 , disable xovr 8 cross over capability recommend value 0 b xovr_0 , disable 1 b xovr_1 , enable xovs 7 cross over status 0 b xovs_0 , non-cross over 1 b xovs_1 , cross over field bits type description ur 5hv ur 5$19 ur )6(/ ur 563' ur 5'83 ur 35(& ur )()' ur ;295 ur ;296 ur 56,, ur 50 ur 3+<$
data sheet 71 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description interrupt status register rsii 6 ro rmii_smii interface 0 b rsll_0 , non rmii_smii interface 1 b rsll_1 , rmii or smii interface used rm 5 repeater mode recommend value 0 b rm_0 , nic/sw 1 b rm_1 , repeater phya 4:0 phy address isr offset reset value interrupt status register 19 h 0000 h field bits type description fru 5hv fru ;29& fru 63'& fru '83& fru 35(& fru /1.& fru 6(55 fru )&$5 fru 7-$% fru 5-$% fru 675(
ADM7001/x data sheet registers description data sheet 72 rev. 1.07, 2005-11-25 receive error counter register field bits type description res 15:10 cor reserved not applicable xovc 9 cross over mode changed 0 b xovc_0 , cross over mode not changed 1 b xovc_1 , cross over mode changed spdc 8 speed changed 0 b spdc_0 , speed not changed 1 b spdc_1 , speed changed dupc 7 duplex changed 0 b dupc_0 , duplex not changed 1 b dupc_1 , duplex changed prec 6 page received 0 b prec_0 , page not received 1 b prec_1 , page received lnkc 5 link status changed 0 b lnkc_0 , link status not changed 1 b lnkc_1 , link status changed serr 4 symbol error 0 b serr_0 , no symbol error 1 b serr_1 , symbol error fcar 3 false carrier note: high whenever link is failed 0 b fcar_0 , no false carrier 1 b fcar_1 , false carrier tjab 2 transmit jabber 0 b tjab_0 , no jabber 1 b tjab_1 , jabber rjab 1 receive jabber 0 b rjab_0 , no jabber 1 b rjab_1 , jabber stre 0 error end of stream 0 b stre_0 , no esd error 1 b stre_1 , esd error recr offset reset value receive error counter register 1d h 0000 h ur (5%
data sheet 73 rev. 1.07, 2005-11-25 ADM7001/x data sheet registers description chip id register field bits type description erb 15:0 ro error counter includes. 1 h 100mfc , 100m false carrier 2 h 100mse , 100m symbol error 3 h 10mtj , 10m transmit jabber 4 h 10mrj , 10m receive jabber 5 h ess , error start of stream 6 h ees , error end of stream cir offset reset value chip id register 1f h 8125 h field bits type description chipid 15:0 ro chipid 15:0 ur &+,3,'
ADM7001/x data sheet electrical characteristics data sheet 74 rev. 1.07, 2005-11-25 5 electrical characteristics 5.1 dc characterization 5.1.1 absolute maximum rating 5.1.2 recommended operating conditions 5.1.2.1 dc characteristics for 2.5 v operation under v cc = 3.0 v ~3.6 v, t j = 0 c ~ 115 c table 23 absolute maximum rating parameter symbol values unit note / test condition min. typ. max. 3.3 v power supply v cc33 3.0 ? 3.6 v ? 2.5 v power supply v cc25 2.25 ? 2.75 v ? input voltage v in -0.3 ? v cc33 + 0.3 v ? output voltage v out -0.25 ? v cc25 + 0.25 v ? storage temperature t stg -55 ? 155 c ? power consumption p c ? ? 0.5 w ? esd rating v esd ? ? 2000 v ? table 24 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. power supply v cc33 3.135 3.3 3.465 v ? input voltage v in 0 ? v cc33 v ? junction operating temperature t j 0 25 115 c ? table 25 dc characteristics for 2.5 v operation parameter symbol values unit note / test condition min. typ. max. input low voltage v il ? ? 0.3 * v cc v cmos input high voltage v ih 0.7 * v cc v ? v cmos output low voltage v ol ? ? 0.4 v cmos output high voltage v oh 2.0 ? ? v cmos input pull-up/down resistance r i ? 75 ? k ? v il = 0 v or v ih = v cc33
data sheet 75 rev. 1.07, 2005-11-25 ADM7001/x data sheet electrical characteristics 5.2 ac characteristics 5.2.1 xi/osci (crystal/oscill ator) timing (i n mii mode) figure 25 crystal/oscillator timing table 26 crystal/oscillator timing parameter symbol values unit note / test condition min. typ. max. xi/osci clock period 1) 1) clock period less then 40ns - 50ppm or greater than 40ns + 50ppm may introduce peer receive crc due to insufficient receive fifo depth. check peer rece ive fifo description to confirm. t xi_per 40.0 - 50 ppm 40.0 40.0 + 50 ppm ns ? xi/osci clock high t xi_hi 14 20.0 ? ns ? xi/osci clock low tx_ilo 14 20.0 ? ns ? xi/osci clock rise time, v il (max) to v ih (min.) t xi_rise ? ? 4 ns ? xi/osci clock fall time, v ih (min.) to v il (max) t xi_fall ? ? 4 ns ?
ADM7001/x data sheet electrical characteristics data sheet 76 rev. 1.07, 2005-11-25 5.3 rmii timing 5.3.1 refclk input timi ng (xi in rmii mode) figure 26 refclk input timing table 27 refclk input timing parameter symbol values unit note / test condition min. typ. max. refclk clock period t in50_per 20.0 - 50 ppm 20.0 20.0 + 50 ppm ns ? refclk clock high t in50_hi 8 10.0 ? ns ? refclk clock low t in50_lo 8 10.0 ? ns ? refclk clock rise time, v il (max) to v ih (min.) t in50_rise ? ? 2 ns ? refclk clock fall time, v ih (min.) to v il (max) t in50_fall ? ? 2 ns ? t_in50_rise t_in50_fall v ih_rmii t_in50_hi t_in50_lo t_in50_per v il_rmii
data sheet 77 rev. 1.07, 2005-11-25 ADM7001/x data sheet electrical characteristics 5.3.2 refclk output timing (clko50 in rmii mode) figure 27 refclk output timing 5.3.3 rmii transmit timing table 28 refclk output timing parameter symbol values unit note / test condition min. typ. max. refclk clock period t out50_per 20.0 - 50 ppm 20.0 20.0 + 50 ppm ns ? refclk clock high t out50_hi 8 10.0 12 ns ? refclk clock low t out50_lo 8 10.0 12 ns ? refclk clock rise time, v il (max) to v ih (min.) t out50_rise ? ? 2 ns ? refclk clock fall time, v ih (min.) to v il (max) t out50_fall ? ? 2 ns ? refclk clock jittering (p-p) t out50_jit ? 0.15 ? ns v t_out50_rise t_out50_fall v ih_rmii t_out50_hi t_out50_lo t_out50_per v il_rmii
ADM7001/x data sheet electrical characteristics data sheet 78 rev. 1.07, 2005-11-25 figure 28 rmii transmit timing 5.3.4 rmii receive timing figure 29 rmii receive timing table 29 rmii transmit timing parameter symbol values unit note / test condition min. typ. max. txd to refclk rising setup time t rt_dsetup 2 ? ? ns ? txd to refclk rising hold time t rt_dhold 2 ? ? ns ? txen asserts to data transmit to medium t rt_txe2mh100 ? ? 235 ns ? txen asserts to data transmit to medium t rt_txe2mh10 ? ? 1550 ns ? txen de-asserts to finish transmitting t rt_txe2ml100 ? ? 260 ns ? txen de-asserts to finish transmitting t rt_txe2ml10 ? ? 1250 ns ?
data sheet 79 rev. 1.07, 2005-11-25 ADM7001/x data sheet electrical characteristics 5.4 mii timing 5.4.1 rxclk clock timing figure 30 rxclk output timing table 30 rmii receive timing parameter symbol values unit note / test condition min. typ. max. signal detected on medium to crsdv high t rr_mh2csh100 ? ? 265 ns ? signal detected on medium to crsdv high t rr_mh2csh10 ? ? 1000 ns ? idle detected on medium to crsdv low t rr_ml2csl100 ? ? 260 ns ? idle detected on medium to crsdv low t rr_ml2csl10 ? ? 570 ns ? crsdv high to receive data on rxd t rr_csh2dat100 ? ? 160 ns ? crsdv high to receive data on rxd t rr_csh2dat10 ? ? 1600 ns ? crsdv toggle to end of data receiving t rr_csl2dat100 ? 160 ? ns ? crsdv toggle to end of data receiving t rr_csl2dat10 ? 1600 ? ns ? refclk rising to rxd/crsdv delay time t rr_ddly ? ? 5 ns ? t_rck_rise t_rck_fall v ih_mii t_rck_hi t_rck_lo t_rck_per v il_mii rxclk
ADM7001/x data sheet electrical characteristics data sheet 80 rev. 1.07, 2005-11-25 table 31 refclk input timing parameter symbol values unit note / test condition min. typ. max. rxclk clock period(100m) note 1) 1) clock period ppm value is highly depended upon peer transmitter clock source skew. t rck_per100 40.0 - 50 ppm 40.0 40.0 + 50 ppm ns ? rxclk clock period(10m) note 2) 2) clock period ppm value is highly depended upon peer transmitter clock source skew. t rck_per10 400.0 - 50 ppm 400.0 400.0 + 50 ppm ns ? rxclk clock high (100m) t rck_hi100 16 ? 24 ? rxclk clock high (10m) t rck_hi10 ? 200 ? ? rxclk clock low (100m) t rck_lo100 16 ? 24 ns ? rxclk clock low (10m) t rck_lo10 ? 200 ? ? rxclk clock rise time, v il (max) to v ih (min.) t rck_rise ? ? 2 ns ? rxclk clock fall time, v ih (min.) to v il (max) t rck_fall ? ? 2 ns ? refclk clock jittering (p-p) t rck_jit ? 0.15 ? ns ?
data sheet 81 rev. 1.07, 2005-11-25 ADM7001/x data sheet electrical characteristics 5.4.2 mii receive timing figure 31 mii receive timing table 32 mii receive timing parameter symbol values unit note / test condition min. typ. max. signal detected on medium to crs high t mr_mh2csh100 ? ? 140 ns ? signal detected on medium to crs high t mr_mh2csh10 ? ? 1450 ns ? signal detected on medium to rxdv high t mr_mh2dat100 ? ? 150 ns ? signal detected on medium to rxdv high t mr_mh2dat10 ? ? 2300 ns ? rxclk rising to data valid delay time t mr_ddly100 10 ? 25 ns ? rxclk rising to data valid delay time t mr_ddly10 10 ? 25 ns ? idle detected on medium to crs low t mr_ml2csl100 ? ? 120 ns ? dle detected on medium to crs low t mr_ml2csl10 ? ? 235 ns ? dle detected on medium to rxdv low t mr_ml2dat100 ? ? 150 ns ? dle detected on medium to rxdv low t mr_ml2dat10 ? ? 1450 ns ? ????t ?? ???3???3 3? ??? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
ADM7001/x data sheet electrical characteristics data sheet 82 rev. 1.07, 2005-11-25 5.4.3 txclk output timing figure 32 txclk output timing 5.4.4 mii transmit timing table 33 txclk output timing parameter symbol values unit note / test condition min. typ. max. txclk clock period (100m) t tck_per100 40.0 - 50 ppm 40.0 40.0 + 50 ppm ns ? txclk clock period (10m) t tck_per10 40.0 - 50 ppm 40.0 40.0 + 50 ppm ns ? txclk clock high (100m) t tck_hi100 16 ? 24 ns ? txclk clock high (10m) t tck_hi10 160 ? 240 ns ? txclk clock low(100m) t tck_lo100 16 ? 24 ns ? txclk clock high (10m) t tck_lo10 160 ? 240 ns ? txclk clock rise time, vil (max) to vih (min) t tck_rise ? ? 2 ns ? txclk clock fall time, vih (min) to vil (max) t tck_fall ? ? 2 ns ? txclk clock jittering (p-p) t tck_jit ? 0.15 ? ns ? t_tck_rise t_tck_fall v ih_mii t_tck_hi t_tck_lo t_tck_per v il_mii txclk
data sheet 83 rev. 1.07, 2005-11-25 ADM7001/x data sheet electrical characteristics figure 33 mii transmit timing 5.5 gpsi timing 5.5.1 gpsi receive timing table 34 mii transmit timing parameter symbol values unit note / test condition min. typ. max. txd to txclk rising setup time t mt_dsetup 10 ? 25 ns ? txd to txclk rising hold time t mt_dhold 10 ? 25 ns ? txen asserts to data transmit to medium (100m) t mt_txe2mh100 ? ? 75 ns ? txen asserts to data transmit to medium (10m) t mt_txe2mh10 ? ? 350 ns ? txen asserts to crs assert (100m half) t mt_txe2csh100 ? ? 15 ns ? txen asserts to crs assert (10m half) t mt_txe2csh10 ? ? 200 ns ? txen de-asserts to finish transmitting (100m) t mt_txe2ml100 ? ? 95 ns ? txen de-asserts to finish transmitting (10m) t mt_txe2ml10 ? ? 660 ns ? txen de-asserts to crs de- asserts (100m) t mt_txe2csl100 ? ? 15 ns ? txen de-asserts to crs de- asserts (10m) t mt_txe2csl10 ? ? 190 ns ? ????t ?? ???33 ? ??? ??? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a ? ? ? ? ? ? ? ? ? ? ? ? ? 3 ? ? 3 a ? ?
ADM7001/x data sheet electrical characteristics data sheet 84 rev. 1.07, 2005-11-25 figure 34 gpsi receive timing 5.5.2 gpsi transmit timing figure 35 gpsi transmit timing table 35 gpsi receive timing parameter symbol values unit note / test condition min. typ. max. 10m receive clock period t gpsi_rck_pe r 100.0 - 50 ppm 100.0 100.0 + 50 ppm ns ? 10m receive clock high t gspi_rck_hi 40 ? ? ns ? 10m receive clock low t gspi_rck_lo 40 ? ? ns ? signal detected on medium to crs high t gr_mh2csh ? ? 1500 ns ? signal detected on medium to data valid t gr_mh2dat ? ? 1600 ns ? rxclk rising to data valid delay time t gr_ddly 40 ? 60 ns ? idle detected on medium to crs low t gr_ml2csl ? ? 230 ns ? ????t ?? ???3???3 3? ??? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t ? ? ? ? ? t ? a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ????t ?? ???33 ? ??? ??? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t ? ? ? ? ? t ? a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a ? ? ? ? ? ? ? ? ? ? ? ? ? 3 ? ? 3 a ? ?
data sheet 85 rev. 1.07, 2005-11-25 ADM7001/x data sheet electrical characteristics 5.6 serial management inte rface (mdc/mdio) timing figure 36 serial management inte rface (mdc/mdio) timing table 36 gpsi transmit timing parameter symbol values unit note / test condition min. typ. max. 10m transmit clock period t gpsi_tck_pe r 100.0 - 50 ppm 100.0 100.0 + 50 ppm ns ? 10m transmit clock high t gspi_tck_hi 40 ? ? ns ? 10m transmit clock low t gspi_tck_lo 40 ? ? ns ? txd to txclk rising setup time t gt_dsetup 40 ? ? ns ? txd to txclk rising hold time t gt_dhold 40 ? ? ns ? txen asserts to data transmit to medium t gt_txe2mh ? ? 150 ns ? txen asserts to crs assert (half) t gt_txe2csh ? ? 10 ns ? txen de-asserts to finish transmitting t gt_txe2ml ? ? 900 ns ? txen de-asserts to crs de- asserts t gt_txecsl ? ? 10 ns ? table 37 serial management inte rface (mdc/mdio) timing parameter symbol values unit note / test condition min. typ. max. mdc period t mdc_per 100 ? ? ns ? mdc high t mdc_hi 40 ? ? ns ? mdc mdio(output) t_mdio_dly mdc mdio(input) t_mdio_setup t_mdio_hold t_mdc_lo t_mdc_per t_mdc_hi
ADM7001/x data sheet electrical characteristics data sheet 86 rev. 1.07, 2005-11-25 5.7 power on configuration timing figure 37 power on configuration timing mdc low t mdc_lo 40 ? ? ns ? mdc to mdio delay time t mdio_dly ? ? 20 ns ? mdio input to mdc setup time t mdio_setup 10 ? ? ns ? mdio input to mdc hold time t mdio_hold 10 ? ? ns ? table 38 power on configuration timing parameter symbol values unit note / test condition min. typ. max. 3.3v power good to 2.5 v power good t v33_v25 tbd ? ? ms ? hardware reset with device powered up t v25_rst 200 ? ? ms ? hardware reset with clock running t rst_pw 800 ? ? ns ? reset high to configuration setup time t pl_dsetup 200 ? ? ns ? reset high to configuration hold time t pl_dhold 0 ? ? ns ? table 37 serial management interface (mdc/mdio) timing (cont?d) parameter symbol values unit note / test condition min. typ. max. vcc3in reset# t_v25_rst xi/osci t_rst_pw t_pl_dhold t_pl_dsetup pwr on latch vcc25out t_v33_v25
data sheet 87 rev. 1.07, 2005-11-25 ADM7001/x data sheet packaging 6 packaging ADM7001/x, low profile quad fl at package (lqfp) 48 pin figure 38 ADM7001/x,low profile quad flat package (lqfp)
ADM7001/x data sheet packaging data sheet 88 rev. 1.07, 2005-11-25 table 39 dimensions for 100 pin lqfp package symbol millimeter (mm) inch min . typ. max. min. typ. max. a ? ? 1.60 ? ? 0.063 a 1 0.05 ? 0.15 0.002 ? 0.006 a 2 1.35 1.40 1.45 0.053 0.005 0.057 d 9.00 bsc. 0.354 bsc. d 1 7.00 bsc 0.276 bsc. e 9.00 bsc 0.354 bsc. e 1 7.00 bsc 0.276 bsc. r 2 0.08 ? 0.20 0.003 ? 0.008 r 1 0.08 ? ? 0.003 ? ? 0 3.5 7 0 3.5 7 1 0 ? ? 0 ? ? 2 11 12 13 11 12 13 3 11 12 13 11 12 13 c 0.09 ? 0.20 0.004 ? 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref. 0.039 ref. s 0.20 ? ? 0.008 ? ? 32l b 0.30 0.35 0.45 0.012 0.014 0.018 e 0.80 bsc. 0.031 bsc. d 2 5.60 0.220 e 2 5.60 0.220 tolerance of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.10 0.003 ddd 0.20 0.008 44l b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc. 0.020 bsc. d 2 5.00 0197 e 2 5.00 0.197 tolerance of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 48l b 0.17 0.20 0.27 0.007 0.008 0.011
data sheet 89 rev. 1.07, 2005-11-25 ADM7001/x data sheet packaging e 0.50 bsc. 0.020 bsc. d 2 5.50 0.217 e 2 5.50 0.217 tolerance of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 table 39 dimensions for 100 pin lqfp package (cont?d) symbol millimeter (mm) inch
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